Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46460 )
Change subject: soc/intel: drop unneeded ISST configuration code ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@16 PS6, Line 16: OS to not enable HWP if that is desired.
Please also mention the other bits that were set by the dropped […]
I confirmed this on CML-U (Clevo L141CU), KBL-H (Smc X11SSM-F) and SKL-U (Acer ES1-572) by printing the MSR in bootblock. In all three cases MSR 0x1aah is 0x1cc0
Cold boot from fresh flash without AC attached ofc.
where in all cases the bits were set after a cold boot (fresh flash without AC attached)
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@19 PS6, Line 19: , as well as the devicetree option
I don't see that.
Done
https://review.coreboot.org/c/coreboot/+/46460/6//COMMIT_MSG@21 PS6, Line 21: explicitly disabling
Are there any?
neither the one or the other. I checked this but forgot to remove that paragraph
-
Michael Niewöhner (Code Review)