Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Werner Zeh (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Patrick Rudolph.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62566/comment/eaf9b474_ca80bc67 
PS2, Line 15: Now, in this scenario, the SPI
            : flash linear address range is not registered as a resource (since the
            : common SPI driver in src/soc/intel/common/block/spi is shared across
            : multiple SPI controllers and therefore cannot distinguish where the
            : flash is actually located at)
> Actually, I'm not sure what would happen on systems without SPI flash. […]

Having boot firmware on eMMC wouldn't be such an issue even in uncached case I guess since eMMC provides a way more faster interface.
The case I was facing hurts so bad because I can only offer a 20 MHz single SPI channel.
Maybe the LPC/eSPI driver could be a good place for this resource. There is a common LPC driver for it and there is usually just one eSPI controller around. Nevertheless it is not 100% accurate because the flash is physically attached to the fast-SPI controller. Maybe we really should add jet another common driver just for the fast-SPI controller.