Hello Varun Joshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to review the following change.
Change subject: mb/google/deltaur:Memory config changes for deltan ......................................................................
mb/google/deltaur:Memory config changes for deltan
SODIMM Changes for Deltan
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc M src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h A src/mainboard/google/deltaur/variants/deltan/memory.c 9 files changed, 182 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/1
diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index a913c75..5d758aa 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -8,6 +8,7 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += ec.c
+romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += ec.c
diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c new file mode 100644 index 0000000..f699bec --- /dev/null +++ b/src/mainboard/google/deltaur/romstage.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/variants.h> +#include <fsp/soc_binding.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/meminit_tgl.h> +#include <soc/romstage.h> +#include <variant/gpio.h> + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + variant_memory_init(mem_cfg); +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc index 937cb46..a98feaa 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc @@ -9,3 +9,7 @@ ramstage-y += gpio.c
verstage-y += gpio.c + +romstage-y += memory.c + +smm-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index e6092b6..08ace41 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -27,10 +27,15 @@ #define GPIO_MEM_CONFIG_3 GPP_F14 #define GPIO_MEM_CONFIG_4 GPP_F15
+/* DQ Memory Interleaved */ +#define MEMORY_INTERLEAVED GPP_E3
const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); struct cros_gpio; const struct cros_gpio *override_cros_gpios(size_t *num);
+/* DRAM population strap (value 0=fully-populated, 1=half-populated) */ +#define GPIO_MEM_CH_SEL GPP_A17 + #endif diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 1d8a934..8483145 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -8,6 +8,7 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> +#include <soc/meminit_tgl.h> #include <stddef.h> #include <vendorcode/google/chromeos/chromeos.h>
@@ -21,4 +22,8 @@
const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct mb_lpddr4x_cfg *variant_memory_params(void); +int variant_memory_sku(void); +void variant_memory_init(FSP_M_CONFIG*); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/deltaur/variants/baseboard/memory.c b/src/mainboard/google/deltaur/variants/baseboard/memory.c new file mode 100644 index 0000000..742e566 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/baseboard/memory.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + + +static const struct mb_lpddr4x_cfg baseboard_memcfg = { + + /* DQ byte map */ + .dq_map = { + { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 7, 2, 6, 3, 5, 1, 4, 0, /* Byte 2 */ + 10, 8, 9, 11, 15, 12, 14, 13 }, /* Byte 3 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 4 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 5 */ + { 7, 0, 1, 6, 5, 4, 2, 3, /* Byte 6 */ + 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ + 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ + { 3, 2, 1, 0, 7, 4, 5, 6, /* Byte 4 */ + 15, 14, 13, 12, 8, 9, 10, 11 }, /* Byte 5 */ + { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ + 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + .ect = 0, /* Disable Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + const struct mb_lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = variant_memory_sku(), + }; + bool half_populated = gpio_get(GPIO_MEM_CH_SEL); + meminit_lpddr4x_dimm0(mem_cfg, board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc index ea0d5f0..94d4bfd 100644 --- a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc @@ -6,4 +6,11 @@ ##
bootblock-y += gpio.c + ramstage-y += gpio.c + +romstage-y += gpio.c + +romstage-y += memory.c + +verstage-y += gpio.c diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h index a1e3789..382f313 100644 --- a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h +++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h @@ -9,6 +9,7 @@
#include <baseboard/gpio.h>
-/* Copied from baseboard and may need to change for the new variant. */ +/* DQ Memory Interleaved */ +#define MEMORY_INTERLEAVED GPP_E3
#endif diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c new file mode 100644 index 0000000..730ddc7 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/meminit_tgl.h> +#include <soc/romstage.h> + + +static const struct mb_lpddr4x_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + { 10, 15, 11, 14, 13, 8, 12, 9, /* Byte 0 */ + 3, 5, 1, 0, 4, 7, 2, 6 }, /* Byte 1 */ + { 15, 8, 11, 13, 10, 12, 14, 9, /* Byte 2 */ + 1, 6, 2, 4, 7, 5, 3, 0 }, /* Byte 3 */ + { 7, 2, 6, 3, 4, 0, 5, 1, /* Byte 4 */ + 14, 10, 15, 11, 9, 13, 8, 12 }, /* Byte 5 */ + { 8, 10, 14, 12, 9, 13, 11, 15, /* Byte 6 */ + 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ + { 12, 14, 10, 11, 15, 13, 9, 8, /* Byte 0 */ + 0, 6, 2, 7, 3, 5, 1, 4 }, /* Byte 1 */ + { 10, 9, 14, 12, 11, 8, 15, 13, /* Byte 2 */ + 7, 3, 1, 4, 6, 2, 0, 5 }, /* Byte 3 */ + { 10, 9, 13, 12, 8, 14, 11, 15, /* Byte 4 */ + 5, 4, 0, 2, 7, 3, 6, 1 }, /* Byte 5 */ + { 15, 9, 11, 13, 10, 14, 8, 12, /* Byte 6 */ + 7, 3, 0, 4, 2, 5, 1, 6 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 1, 0 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } + }, + + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa2}, + }, + /* Baseboard rcomp resistor */ + .rcomp_resistor = 100, + + .ect = 0, /* Disable Early Command Training */ +}; + +void variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + struct mb_lpddr4x_cfg new_board_cfg_ddr4; + + memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg)); + + new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); + + tigerlake_memcfg_init(mem_cfg, &new_board_cfg_ddr4); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur:Memory config changes for deltan ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... PS1, Line 27: void variant_memory_init(FSP_M_CONFIG*); "(foo*)" should be "(foo *)"
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... PS1, Line 27: void variant_memory_init(FSP_M_CONFIG*); function definition argument 'FSP_M_CONFIG*' should also have an identifier name
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... PS1, Line 17: .dq_map = { code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/1/src/mainboard/google/deltau... PS1, Line 17: .dq_map = { please, no spaces at the start of a line
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 2:
This change is ready for review.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 15: smm-y += gpio.c remove this.
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 39: #define GPIO_MEM_CH_SEL GPP_A17 This pin is NC in GPIO table. Do we use this?
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 69: bool half_populated = gpio_get(GPIO_MEM_CH_SEL); This is not used for half channel. I don't think we have signal channel sku.
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 13: #define MEMORY_INTERLEAVED GPP_E3 Already in baseboard, not needed.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 48: .spd[1] = { Spd[2] and address 0xa4? We can reference Sarien or not?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#3).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c 8 files changed, 178 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 17: .dq_map = { code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 17: .dq_map = { please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 54: .read_type = READ_SMBUS, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 54: .read_type = READ_SMBUS, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 55: .spd_spec = {.spd_smbus_address[0] = 0xa0, code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/3/src/mainboard/google/deltau... PS3, Line 55: .spd_spec = {.spd_smbus_address[0] = 0xa0, please, no space before tabs
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#4).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/4
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#5).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/5
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/5/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/5/src/mainboard/google/deltau... PS5, Line 14: remove src/mainboard/google/deltaur/variants/baseboard/Makefile.inc has multiple final newlines. test failed
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#6).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c 8 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/6
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#7).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 9 files changed, 265 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/7
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#8).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/baseboard/memory.c M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 9 files changed, 265 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/8
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Varun Joshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#9).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 175 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/9
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 15: smm-y += gpio.c
remove this.
Done
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 39: #define GPIO_MEM_CH_SEL GPP_A17
This pin is NC in GPIO table. […]
This was used by lpddr implementation, Used for halfpopulated in baseboard memory.c. Do we remove half populated altogether for deltaur?
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 13: #define MEMORY_INTERLEAVED GPP_E3
Already in baseboard, not needed.
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 69: bool half_populated = gpio_get(GPIO_MEM_CH_SEL);
This is not used for half channel. I don't think we have signal channel sku.
This was used by lpddr implementation, Used for halfpopulated in baseboard memory.c. Do we remove half populated altogether for deltaur?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 39: #define GPIO_MEM_CH_SEL GPP_A17
This was used by lpddr implementation, Used for halfpopulated in baseboard memory.c. […]
SODIMM not needed and for solder down, I think all sku are dual channel. We can add this if needed.
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 69: bool half_populated = gpio_get(GPIO_MEM_CH_SEL);
This was used by lpddr implementation, Used for halfpopulated in baseboard memory.c. […]
see previous comment.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2}, Change to address[3]=0xa4. Please refer Furquan comment.
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
Change to address[3]=0xa4. Please refer Furquan comment.
Okay, and the dq mapping above still holds good? Now that only 2 fspm DqMapCpu2DramCh0/1 to use?.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
Okay, and the dq mapping above still holds good? Now that only 2 fspm DqMapCpu2DramCh0/1 to use?.
Yes, I checked Sarien. The same two CH for DQS map. Because we use CH0 and CH1. And SPD address is for CH0 dimm1/2 CH1 dimm1/2. 👍
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
Yes, I checked Sarien. The same two CH for DQS map. Because we use CH0 and CH1. […]
It should be following for delatn with DIMM1 and DIMM2 at ch0 and ch1 respectively right? spd_smbus_address[0] = 0xa0; spd_smbus_address[1] = NULL; spd_smbus_address[2] = 0xa2; spd_smbus_address[3] = NULL
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
It should be following for delatn with DIMM1 and DIMM2 at ch0 and ch1 respectively right? […]
Correction, should be the below right? spd_smbus_address[0] = 0xa0; spd_smbus_address[1] = NULL; spd_smbus_address[2] = NULL; spd_smbus_address[3] = oxa2;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
Correction, should be the below right? […]
I have updated the header to make this easier to use: https://review.coreboot.org/c/coreboot/+/39866/5/src/soc/intel/tigerlake/inc...
It should be: smbus_info[0].addr_dimm0 = ...; // Channel 0 Dimm 0 smbus_info[1].addr_dimm0 = ...; // Channel 1 Dimm 0
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#10).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/deltan/memory.c 2 files changed, 27 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/10
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#12).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/12/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/12/src/mainboard/google/delta... PS12, Line 26: trailing whitespace
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#13).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/13
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#14).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/14
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 57: .smbus_info[1] = {.addr_dimm0 = 0xa2, Address a4? 0xa2 is for CH0 dimm1, you can check this.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 14:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 39: #define GPIO_MEM_CH_SEL GPP_A17 I can help confirm this with HW. But I think we don't need this.
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 27: void variant_memory_init(FSP_M_CONFIG *mem_cfg); weak this.
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 12: romstage-y += gpio.c this is not belong this patch.
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 16: verstage-y += gpio.c same above.
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 49: int __weak variant_memory_sku(void) not weak here.
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 61: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg) same above.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#15).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 173 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/15
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 15:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/15/src/mainboard/google/delta... PS15, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
https://review.coreboot.org/c/coreboot/+/39848/15/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/15/src/mainboard/google/delta... PS15, Line 44: const struct lpddr4x_cfg * variant_memory_params(void) "foo * bar" should be "foo *bar"
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#16).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read spd from SMBus
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 173 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/16
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/16/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/16/src/mainboard/google/delta... PS16, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
(6 comments)
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 27: void variant_memory_init(FSP_M_CONFIG *mem_cfg);
weak this.
Done
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 16: verstage-y += gpio.c
same above.
Done
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 16: verstage-y += gpio.c
same above.
Done
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/9/src/mainboard/google/deltau... PS9, Line 56: .spd_smbus_address[1] = 0xa2},
I have updated the header to make this easier to use: https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 49: int __weak variant_memory_sku(void)
not weak here.
Done
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 61: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg)
same above.
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 12: romstage-y += gpio.c
this is not belong this patch.
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 57: .smbus_info[1] = {.addr_dimm0 = 0xa2,
Address a4? 0xa2 is for CH0 dimm1, you can check this.
We have 2 i2c addresses for DIMM, 0xa0 and 0xa2 in the deltan schematics. Can you confirm if it is 0xa4?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
Patch Set 16:
(1 comment)
I am looking for EDS, but not found yet. If you already for this, it's fine 💯
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
DIMM1 is means 0xa4? Not sure how to calculate this correctly. SA0 SA1 SA2 1. 0. 0
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 16:
Patch Set 16:
DIMM1 is means 0xa4? Not sure how to calculate this correctly. SA0 SA1 SA2
- 0
Sorry DIMM2.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/17/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/17/src/mainboard/google/delta... PS17, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/18/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/18/src/mainboard/google/delta... PS18, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 18:
Sorry, confirm with HW. Please check the P.24 *DIMM3, we use that config. So based on this setting. 1010 + 010, address should be 0xa4.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG@10 PS18, Line 10: spd SPD
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG@10 PS18, Line 10: Configure memory to read spd from SMBus Please add a dot/period at the end of sentences.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#19).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD from SMBus.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 192 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/19
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 19:
(31 comments)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 21: { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 21: { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 23: { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 23: { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 24: { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 24: { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 25: { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 25: { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 26: { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 26: { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 31: { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 31: { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 32: { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 32: { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 33: { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 33: { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 34: { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 34: { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 35: { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 35: { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 36: { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 36: { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 37: { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 37: { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 44: { 1, 0 , 1, 0 , 0, 1 , 1, 0 }, space prohibited before that ',' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 44: { 1, 0 , 1, 0 , 0, 1 , 1, 0 }, space prohibited before that ',' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 44: { 1, 0 , 1, 0 , 0, 1 , 1, 0 }, space prohibited before that ',' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 45: { 1, 0 , 1, 0 , 1, 0 , 1, 0 } space prohibited before that ',' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 45: { 1, 0 , 1, 0 , 1, 0 , 1, 0 } space prohibited before that ',' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/39848/19/src/mainboard/google/delta... PS19, Line 45: { 1, 0 , 1, 0 , 1, 0 , 1, 0 } space prohibited before that ',' (ctx:WxW)
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#20).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD from SMBus.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 192 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/20
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/20/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/20/src/mainboard/google/delta... PS20, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 21:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG@10 PS18, Line 10: Configure memory to read spd from SMBus
Please add a dot/period at the end of sentences.
Done
https://review.coreboot.org/c/coreboot/+/39848/18//COMMIT_MSG@10 PS18, Line 10: spd
SPD
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 21:
Patch Set 18:
Sorry, confirm with HW. Please check the P.24 *DIMM3, we use that config. So based on this setting. 1010 + 010, address should be 0xa4.
Set CH1-DIMM0 to 0xa4.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 21:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 14: nits: remove one line.
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 9: nits:remove the warp line. or add warp line in another makefile.
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 13: nit: remove one line.
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 43: nit:remove this line.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg);
Using weak declarations can have unintended link defects
remove weak here can work fine?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 22:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 61: bool const bool
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 77: }; GPIO_MEM_CONFIG_4 ?
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 89: const bool
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 89:
const bool
Also shouldn't this read ONE_DIMM# to figure this out?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#23).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 193 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/23
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/23/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/23/src/mainboard/google/delta... PS23, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#24).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 193 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/24
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/24/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/24/src/mainboard/google/delta... PS24, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/25/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/25/src/mainboard/google/delta... PS25, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/26/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/26/src/mainboard/google/delta... PS26, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 26:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 77: };
GPIO_MEM_CONFIG_4 ?
Done
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 89:
Also shouldn't this read ONE_DIMM# to figure this out?
This was based on GPIO_MEM_CH_SEL earlier, which is not there in schematics.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 89:
This was based on GPIO_MEM_CH_SEL earlier, which is not there in schematics.
@Tim, we don't have one dimm config at all.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 89:
@Tim, we don't have one dimm config at all.
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#27).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/27
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... PS27, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 27:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... PS27, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg);
Using weak declarations can have unintended link defects
Can you remove this weak? I think you already implement in each memory.c so this can remove.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/28/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/28/src/mainboard/google/delta... PS28, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#29).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/29
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 29:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/29/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/29/src/mainboard/google/delta... PS29, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg); Using weak declarations can have unintended link defects
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#30).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/30
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 14:
nits: remove one line.
Done
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/27/src/mainboard/google/delta... PS27, Line 27: void __weak variant_memory_init(FSP_M_CONFIG *mem_cfg);
Can you remove this weak? I think you already implement in each memory.c so this can remove.
Done
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 9:
nits:remove the warp line. or add warp line in another makefile.
Done
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 13:
nit: remove one line.
Done
https://review.coreboot.org/c/coreboot/+/39848/21/src/mainboard/google/delta... PS21, Line 43:
nit:remove this line.
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39848/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/1//COMMIT_MSG@7 PS1, Line 7: mb/google/deltaur:Memory config changes for deltan
Please add a space after the colon.
Done
https://review.coreboot.org/c/coreboot/+/39848/1//COMMIT_MSG@10 PS1, Line 10:
Same comments as in https://review.coreboot.org/c/coreboot/+/39847 apply.
Done
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 39: #define GPIO_MEM_CH_SEL GPP_A17
SODIMM not needed and for solder down, I think all sku are dual channel. We can add this if needed.
Done
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 69: bool half_populated = gpio_get(GPIO_MEM_CH_SEL);
see previous comment.
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/5/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/baseboard/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/39848/5/src/mainboard/google/deltau... PS5, Line 14:
remove src/mainboard/google/deltaur/variants/baseboard/Makefile.inc has multiple final newlines. […]
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 39: #define GPIO_MEM_CH_SEL GPP_A17
I can help confirm this with HW. But I think we don't need this.
Done
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 57: .smbus_info[1] = {.addr_dimm0 = 0xa2,
We have 2 i2c addresses for DIMM, 0xa0 and 0xa2 in the deltan schematics. […]
Changed to 0xA4
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/22/src/mainboard/google/delta... PS22, Line 61: bool
const bool
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/2/src/mainboard/google/deltau... PS2, Line 48: .spd[1] = {
Spd[2] and address 0xa4? We can reference Sarien or not?
Done
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(1 comment)
a
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/14/src/mainboard/google/delta... PS14, Line 57: .smbus_info[1] = {.addr_dimm0 = 0xa2,
Changed to 0xA4
Done
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... PS30, Line 8: #include <fsp/soc_binding.h> : #include <gpio.h> : #include <soc/gpio.h> need these?
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... PS30, Line 13: #include <variant/gpio.h> do we need this?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#31).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 182 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/31
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 31:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... PS30, Line 8: #include <fsp/soc_binding.h> : #include <gpio.h> : #include <soc/gpio.h>
need these?
Done. Not needed
https://review.coreboot.org/c/coreboot/+/39848/30/src/mainboard/google/delta... PS30, Line 13: #include <variant/gpio.h>
do we need this?
Done. Not needed
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 31:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/12/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/12/src/mainboard/google/delta... PS12, Line 26:
trailing whitespace
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... PS34, Line 26: int variant_memory_sku(void); This doesn't need to be exported, Deltan doesn't have this function.
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... PS34, Line 70: int This can then be 'static int'
Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#35).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 181 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/35
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 35:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... PS34, Line 26: int variant_memory_sku(void);
This doesn't need to be exported, Deltan doesn't have this function.
Done
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/34/src/mainboard/google/delta... PS34, Line 70: int
This can then be 'static int'
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 35: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 35: Code-Review+2
Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#36).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 181 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/36
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 36: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 36:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/36/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/36/src/mainboard/google/delta... PS36, Line 8: #include <soc/meminit.h> maybe remove this? you put this in baseboard/variants.h
Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#37).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/37
Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#38).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map, rcomp value based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/38
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 37: Code-Review+2
Finally, thanks for the working 👍
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 38:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/36/src/mainboard/google/delta... File src/mainboard/google/deltaur/romstage.c:
https://review.coreboot.org/c/coreboot/+/39848/36/src/mainboard/google/delta... PS36, Line 8: #include <soc/meminit.h>
maybe remove this? you put this in baseboard/variants. […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 38: Code-Review+2
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 38:
Patch Set 37: Code-Review+2
Finally, thanks for the working 👍
Thank you all for the help!
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 38:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... PS38, Line 44: 0 CB:40023 noted that we should set this value to 1 to prep for an upcoming MRC kit that requires ECT to be enabled.
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... PS38, Line 61: ect CB:40023 noted that we should set this value to 1 to prep for an upcoming MRC kit that requires ECT to be enabled.
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 38:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltan/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... PS38, Line 44: 0
CB:40023 noted that we should set this value to 1 to prep for an upcoming MRC kit that requires ECT […]
Ack
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... File src/mainboard/google/deltaur/variants/deltaur/memory.c:
https://review.coreboot.org/c/coreboot/+/39848/38/src/mainboard/google/delta... PS38, Line 61: ect
CB:40023 noted that we should set this value to 1 to prep for an upcoming MRC kit that requires ECT […]
Ack
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 40: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 41:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG@9 PS41, Line 9: rcomp Actually, I don't see any rcomp settings here.
Hello build bot (Jenkins), Anil Kumar K, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Kevin Chowski, Anil Kumar K, Varun Joshi, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39848
to look at the new patch set (#42).
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39848/42
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG@9 PS41, Line 9: rcomp
Actually, I don't see any rcomp settings here.
this was removed later. Updated.
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/41//COMMIT_MSG@9 PS41, Line 9: rcomp
this was removed later. Updated.
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG@7 PS42, Line 7: mb/google/deltaur: Update onboard memory config … for Deltan?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG@7 PS42, Line 7: mb/google/deltaur: Update onboard memory config
… for Deltan?
The config is updated for both deltan & deltaur. One is DDR4, the other is LPDDR4.
Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39848/42//COMMIT_MSG@7 PS42, Line 7: mb/google/deltaur: Update onboard memory config
The config is updated for both deltan & deltaur. One is DDR4, the other is LPDDR4.
Ack
Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics. Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi varun.joshi@intel.corp-partner.google.com Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/memory.c 8 files changed, 177 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index a913c75..5d758aa 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -8,6 +8,7 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += ec.c
+romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += ec.c
diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c new file mode 100644 index 0000000..2d73629 --- /dev/null +++ b/src/mainboard/google/deltaur/romstage.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + variant_memory_init(mem_cfg); +} diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index e6092b6..e6b23e6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -27,6 +27,8 @@ #define GPIO_MEM_CONFIG_3 GPP_F14 #define GPIO_MEM_CONFIG_4 GPP_F15
+/* DQ Memory Interleaved */ +#define MEMORY_INTERLEAVED GPP_E3
const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 1d8a934..a1f1b22 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -8,6 +8,7 @@ #define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h> +#include <soc/meminit.h> #include <stddef.h> #include <vendorcode/google/chromeos/chromeos.h>
@@ -21,4 +22,7 @@
const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct lpddr4x_cfg *variant_memory_params(void); +void variant_memory_init(FSP_M_CONFIG *mem_cfg); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc index ea0d5f0..bad6b24 100644 --- a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc @@ -7,3 +7,4 @@
bootblock-y += gpio.c ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c new file mode 100644 index 0000000..90fa642 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_ddr4_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ + { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ + { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ + { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ + { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ + { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ + { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ + { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ + }, + + [1] = { + { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ + { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ + { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ + { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ + { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ + { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ + { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ + { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 1, 0, 1, 0, 0, 1, 1, 0 }, + { 1, 0, 1, 0, 1, 0, 1, 0 } + }, + + .ect = 0, /* Disable Early Command Training */ +}; + +void variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + const struct spd_info spd_info = { + .smbus_info[0] = {.addr_dimm0 = 0xa0, + .addr_dimm1 = 0 }, + .smbus_info[1] = {.addr_dimm0 = 0xa4, + .addr_dimm1 = 0 }, + }; + const bool half_populated = false; + struct mb_ddr4_cfg new_board_cfg_ddr4; + + memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg)); + + new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); + + meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); +} diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc index ea0d5f0..bad6b24 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc @@ -7,3 +7,4 @@
bootblock-y += gpio.c ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c new file mode 100644 index 0000000..c2df467 --- /dev/null +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <variant/gpio.h> + +static const struct lpddr4x_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 0, /* Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +static int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void variant_memory_init(FSP_M_CONFIG *mem_cfg) +{ + const struct lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct spd_info spd_info = { + .md_spd_loc = SPD_CBFS, + .cbfs_index = variant_memory_sku(), + }; + const bool half_populated = false; + meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); +}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39848 )
Change subject: mb/google/deltaur: Update onboard memory config ......................................................................
Patch Set 43:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2299 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2298 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2297
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Bora Guvendik (Code Review)
-
build bot (Jenkins) (Code Review)
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EricR Lai (Code Review)
-
Furquan Shaikh (Code Review)
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Martin Roth (Code Review)
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Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)
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Varun Joshi (Code Review)