Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock

[Ethan Tsao (Code Review)]

Attention is currently required from: Felix Singer, Jamie Ryu, Wonkyu Kim, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Angel Pons, Raj Astekar.
Ethan Tsao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 )

Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
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Patch Set 10:

(1 comment)

File src/soc/intel/meteorlake/include/soc/espi.h:

https://review.coreboot.org/c/coreboot/+/62772/comment/019196cc_be173979 
PS7, Line 24: #define PCCTL			0xE0 /* PCI Clock Control */
> Does this register actually exist? It only seems to exist on platforms that have LPC.

Ack