Patch merged into coreboot/master: google/eve: Fix FPC support

the following patch was just integrated into master:
commit 6c8238521eaf2216c9a41502be1cb2703a0d6f3e
Author: Duncan Laurie 
Date:   Fri Feb 17 17:24:12 2017 -0800

google/eve: Fix FPC support

Currently UART0 GPIOs are being put into native mode during FSP-S
    stage, so have ramstage re-configure them back to regular GPIO mode.

GPP_C8 does not seem to be functioning properly when routed to the
    APIC, possibly due to the UART0 being enabled even though it is unused,
    which is required because UART0 is PCI 1e.0 and so must be present for
    other 1e.x functions to be enumerated.  Instead, use this pin as a GPIO
    interrupt so it will be routed through the GPIO controller at IRQ 14.

GPP_C9 was inverted and was only working because the pin was being
    re-configured in FSP-S.

Also export the reset gpio as a device property so it can be used by
    the kernel driver, which will stop it from complaining at boot.

BUG=chrome-os-partner:61233
    TEST=verify that the interrupt and device is functional in the OS

Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://review.coreboot.org/18395
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh

See https://review.coreboot.org/18395 for details.

-gerrit