[L] Change in coreboot[master]: haswell NRI: Add DDR3 JEDEC reset and init

[Bill XIE (Code Review)]

Bill XIE has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/77055?usp=email )

Change subject: haswell NRI: Add DDR3 JEDEC reset and init
......................................................................

haswell NRI: Add DDR3 JEDEC reset and init

Implement JEDEC reset and init sequence for DDR3. The MRS commands are
issued through the REUT (Robust Electrical Unified Testing) hardware.

Original-Change-Id: I2a0c066537021b587599228086727cb1e041bff5
Original-Signed-off-by: Angel Pons 
Signed-off-by: Bill XIE 
Change-Id: I7f47090f95d9ac7e83d6a8fe9faefc10da92b719
---
M src/northbridge/intel/haswell/native_raminit/Makefile.inc
A src/northbridge/intel/haswell/native_raminit/ddr3.c
M src/northbridge/intel/haswell/native_raminit/io_comp_control.c
A src/northbridge/intel/haswell/native_raminit/jedec_reset.c
M src/northbridge/intel/haswell/native_raminit/raminit_main.c
M src/northbridge/intel/haswell/native_raminit/raminit_native.h
M src/northbridge/intel/haswell/native_raminit/reg_structs.h
A src/northbridge/intel/haswell/native_raminit/reut.c
M src/northbridge/intel/haswell/registers/mchbar.h
M src/southbridge/intel/lynxpoint/pch.h
10 files changed, 843 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/77055/5