[M] Change in coreboot[master]: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW

[Felix Held (Code Review)]

Attention is currently required from: Johnny Lin, Christian Walter, Arthur Heymans, Kyösti Mälkki, Tim Chu.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70270 )

Change subject: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW
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Patch Set 7:

(1 comment)

File src/soc/intel/xeon_sp/cpx/soc_util.c:

https://review.coreboot.org/c/coreboot/+/70270/comment/990d2bb7_6b023ea4 
PS7, Line 72: 		ioapic_id += 1;
> ICH4 and iCH7 claim upper 4 bits Reserved, RW with default 0. […]

iirc the ioapic spec only specifies a 4 bit field for this and has the other bits marked as reserved. nowadays, just start counting the ioapic ids from 0 can be done and when not counting the iooapic ids from MAX_CPUS (which should be the largest lapic number) this shouldn't really be an issue. on amd/cezanne the ioapic id is 8 bits wide, but the lowest 4 bits are more than sufficient after assigning ioapic number from 0 on.