HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45272 )
Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax ......................................................................
nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax
Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45272/1
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..cdc77b5f 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -8,13 +8,13 @@ Method (_OSC, 4) { /* Check for proper PCI/PCIe UUID */ - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return(Arg3) } Else { CreateDWordField(Arg3, 0, CDW1) - Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 + CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } } @@ -52,22 +52,22 @@ Method (_CRS, 0, Serialized) { //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(_SB.PCI0.LPCB.RCBA, 14, RBR0) + //RBR0 = _SB.PCI0.LPCB.RCBA << 14
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(_SB.PCI0.MCHC.MHBR, 14, MBR0) + //MBR0 = _SB.PCI0.MCHC.MHBR << 14
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(_SB.PCI0.MCHC.DMBR, 12, DBR0) + //DBR0 = _SB.PCI0.MCHC.DMBR << 12
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(_SB.PCI0.MCHC.EPBR, 12, EBR0) + //EBR0 = _SB.PCI0.MCHC.EPBR << 12
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(_SB.PCI0.MCHC.PXBR, 26, PBR0) + //PBR0 = _SB.PCI0.MCHC.PXBR << 26
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, _SB.PCI0.MCHC.PXSZ, PSZ0) + //PSZ0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ
Return(PDRS) }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45272
to look at the new patch set (#2).
Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax ......................................................................
nb/intel/i945/acpi: Convert i945.asl to ASL+ Syntax
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45272/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45272
to look at the new patch set (#3).
Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax ......................................................................
nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45272/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45272 )
Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45272 )
Change subject: nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax ......................................................................
nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/45272 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/i945/acpi/i945.asl 1 file changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..cdc77b5f 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -8,13 +8,13 @@ Method (_OSC, 4) { /* Check for proper PCI/PCIe UUID */ - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return(Arg3) } Else { CreateDWordField(Arg3, 0, CDW1) - Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 + CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } } @@ -52,22 +52,22 @@ Method (_CRS, 0, Serialized) { //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - //ShiftLeft(_SB.PCI0.LPCB.RCBA, 14, RBR0) + //RBR0 = _SB.PCI0.LPCB.RCBA << 14
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - //ShiftLeft(_SB.PCI0.MCHC.MHBR, 14, MBR0) + //MBR0 = _SB.PCI0.MCHC.MHBR << 14
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - //ShiftLeft(_SB.PCI0.MCHC.DMBR, 12, DBR0) + //DBR0 = _SB.PCI0.MCHC.DMBR << 12
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - //ShiftLeft(_SB.PCI0.MCHC.EPBR, 12, EBR0) + //EBR0 = _SB.PCI0.MCHC.EPBR << 12
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - //ShiftLeft(_SB.PCI0.MCHC.PXBR, 26, PBR0) + //PBR0 = _SB.PCI0.MCHC.PXBR << 26
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - //ShiftLeft(0x10000000, _SB.PCI0.MCHC.PXSZ, PSZ0) + //PSZ0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ
Return(PDRS) }
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)