Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30897
Change subject: mb/clevo/n130wu: Add variants ......................................................................
mb/clevo/n130wu: Add variants
Devices: - N130BU / N131BU
Change-Id: I1e771c48409f79edb1355af6992ba43269b98b8e Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M src/mainboard/clevo/n130wu/Kconfig M src/mainboard/clevo/n130wu/Kconfig.name A src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt A src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb 4 files changed, 271 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30897/1
diff --git a/src/mainboard/clevo/n130wu/Kconfig b/src/mainboard/clevo/n130wu/Kconfig index 49a6b56..cb90d01 100644 --- a/src/mainboard/clevo/n130wu/Kconfig +++ b/src/mainboard/clevo/n130wu/Kconfig @@ -1,4 +1,4 @@ -if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU +if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU || BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,10 +23,13 @@
config VARIANT_DIR string + default "n13xbu" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "n13xwu" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config MAINBOARD_PART_NUMBER string + default "N130BU" if BOARD_CLEVO_N130BU + default "N131BU" if BOARD_CLEVO_N131BU default "N130WU" if BOARD_CLEVO_N130WU default "N131WU" if BOARD_CLEVO_N131WU
@@ -44,6 +47,7 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex + default 0x1303 if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default 0x1313 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config CONSOLE_POST @@ -60,6 +64,7 @@
config MAX_CPUS int + default 4 if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default 8 if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config DIMM_MAX @@ -72,10 +77,12 @@
config VGA_BIOS_FILE string + default "pci8086,5916.rom" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "pci8086,5917.rom" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config VGA_BIOS_ID string + default "8086,5916" if BOARD_CLEVO_N130BU || BOARD_CLEVO_N131BU default "8086,5917" if BOARD_CLEVO_N130WU || BOARD_CLEVO_N131WU
config PXE_ROM_ID diff --git a/src/mainboard/clevo/n130wu/Kconfig.name b/src/mainboard/clevo/n130wu/Kconfig.name index f252f0b..a6c84b9 100644 --- a/src/mainboard/clevo/n130wu/Kconfig.name +++ b/src/mainboard/clevo/n130wu/Kconfig.name @@ -1,3 +1,9 @@ +config BOARD_CLEVO_N130BU + bool "N130BU" + +config BOARD_CLEVO_N131BU + bool "N131BU" + config BOARD_CLEVO_N130WU bool "N130WU"
diff --git a/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt b/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt new file mode 100644 index 0000000..fafa43f --- /dev/null +++ b/src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb b/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb new file mode 100644 index 0000000..d094df5 --- /dev/null +++ b/src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb @@ -0,0 +1,257 @@ +# WIP + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + register "VmxEnable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_E" + register "gpe0_dw1" = "GPP_A" + register "gpe0_dw2" = "GPP_C" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 32A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(32), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable root ports + register "PcieRpEnable[0]" = "1" # TBT + register "PcieRpEnable[1]" = "1" # TBT + register "PcieRpEnable[2]" = "1" # TBT + register "PcieRpEnable[3]" = "1" # TBT + register "PcieRpEnable[4]" = "1" # LAN / Card reader + register "PcieRpEnable[5]" = "1" # WLAN + register "PcieRpEnable[8]" = "1" # SSD PCIEx4 + register "PcieRpEnable[9]" = "1" # SSD PCIEx4 + register "PcieRpEnable[10]" = "1" # SSD PCIEx4 + register "PcieRpEnable[11]" = "1" # SSD PCIEx4 + + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" # TBT + register "PcieRpClkReqSupport[1]" = "1" # TBT + register "PcieRpClkReqSupport[2]" = "1" # TBT + register "PcieRpClkReqSupport[3]" = "1" # TBT + register "PcieRpClkReqSupport[4]" = "1" # LAN / Card reader + register "PcieRpClkReqSupport[5]" = "1" # WLAN + register "PcieRpClkReqSupport[8]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[9]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[10]" = "1" # SSD PCIEx4 + register "PcieRpClkReqSupport[11]" = "1" # SSD PCIEx4 + + # Configure SRCCLKREQ# + register "PcieRpClkReqNumber[0]" = "4" # TBT + register "PcieRpClkReqNumber[1]" = "4" # TBT + register "PcieRpClkReqNumber[2]" = "4" # TBT + register "PcieRpClkReqNumber[3]" = "4" # TBT + register "PcieRpClkReqNumber[4]" = "3" # LAN / Card reader + register "PcieRpClkReqNumber[5]" = "2" # WLAN + register "PcieRpClkReqNumber[8]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[9]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[10]" = "5" # SSD PCIEx4 + register "PcieRpClkReqNumber[11]" = "5" # SSD PCIEx4 + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # PL2 override 44W + register "tdp_pl2_override" = "40" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Processor Gaussian Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30897 )
Change subject: mb/clevo/n130wu: Add variants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30897/1/src/mainboard/clevo/n130wu/variants/... File src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb:
https://review.coreboot.org/#/c/30897/1/src/mainboard/clevo/n130wu/variants/... PS1, Line 1: WIP I am pretty sure most of the devicetree has the same values. I would consider using an overridetree instead.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30897 )
Change subject: mb/clevo/n130wu: Add variants ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30897/1/src/mainboard/clevo/n130wu/variants/... File src/mainboard/clevo/n130wu/variants/n13xbu/devicetree.cb:
https://review.coreboot.org/#/c/30897/1/src/mainboard/clevo/n130wu/variants/... PS1, Line 1: WIP
I am pretty sure most of the devicetree has the same values. […]
I will look into this
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30897
to look at the new patch set (#3).
Change subject: mb/clevo/n130wu: Add variants ......................................................................
mb/clevo/n130wu: Add variants
Devices: - N130BU / N131BU
Change-Id: I1e771c48409f79edb1355af6992ba43269b98b8e Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M src/mainboard/clevo/n130wu/Kconfig M src/mainboard/clevo/n130wu/Kconfig.name A src/mainboard/clevo/n130wu/variants/n13xbu/data.vbt A src/mainboard/clevo/n130wu/variants/n13xbu/overridetree.cb 4 files changed, 128 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30897/3
-
Angel Pons (Code Review) -
Felix Singer (Code Review)