Change in coreboot[master]: mb/siemens/chili: Remove unnecessary device declarations

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48374 )

Change subject: mb/siemens/chili: Remove unnecessary device declarations
......................................................................

mb/siemens/chili: Remove unnecessary device declarations

Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
---
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
2 files changed, 5 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index 196cd81..6bdec65 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -86,8 +86,7 @@
    		register "PcieRpSlotImplemented[5]" = "0"
    	end
    	device pci 1c.6 on		# PCI Express Port 7
-			device pci 00.0 on end	# x1 M.2 (WLAN / BT)
-			register "PcieRpEnable[6]" = "1"
+			register "PcieRpEnable[6]" = "1" # x1 M.2 (WLAN / BT)
    		register "PcieRpSlotImplemented[6]" = "1"
    	end
    	device pci 1c.7 off	end	# PCI Express Port 8
@@ -100,8 +99,7 @@
    	device pci 1d.6 off	end	# PCI Express Port 15
    	device pci 1d.7 off	end	# PCI Express Port 16
    	device pci 1b.0 on		# PCI Express Port 17
-			device pci 00.0 on end	# x4 M.2/M
-			register "PcieRpEnable[16]" = "1"
+			register "PcieRpEnable[16]" = "1" # x4 M.2/M
    		register "PcieClkSrcUsage[7]" = "16"
    		register "PcieClkSrcClkReq[7]" = "7"
    		register "PcieRpSlotImplemented[16]" = "1"
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index 6c5a306..8595ce8 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -112,8 +112,7 @@
    	device pci 19.2 off	end	# UART #2
    	device pci 1a.0 off	end	# eMMC
    	device pci 1c.0 off		# PCI Express Port 1
-			device pci 00.0 on end	# Debug (x1)
-			register "PcieRpEnable[0]" = "0"
+			register "PcieRpEnable[0]" = "0" # Debug (x1)
    		register "PcieClkSrcUsage[2]" = "0"
    		register "PcieClkSrcClkReq[2]" = "2"
    	end
@@ -121,8 +120,7 @@
    	device pci 1c.2 off	end	# PCI Express Port 3
    	device pci 1c.3 off	end	# PCI Express Port 4
    	device pci 1c.4 on		# PCI Express Port 5
-			device pci 00.0 on end	# CORE (x1)
-			register "PcieRpEnable[4]" = "1"
+			register "PcieRpEnable[4]" = "1" # CORE (x1)
    		register "PcieClkSrcUsage[4]" = "4"
    		register "PcieClkSrcClkReq[4]" = "4"
    		register "PcieRpSlotImplemented[4]" = "1"
@@ -157,8 +155,7 @@
    	device pci 1d.6 off	end	# PCI Express Port 15
    	device pci 1d.7 off	end	# PCI Express Port 16
    	device pci 1b.0 on		# PCI Express Port 17
-			device pci 00.0	on end	# NVMe (x4)
-			register "PcieRpEnable[16]" = "1"
+			register "PcieRpEnable[16]" = "1" # NVMe (x4)
    		register "PcieClkSrcUsage[7]" = "16"
    		register "PcieClkSrcClkReq[7]" = "7"
    		register "PcieRpSlotImplemented[16]" = "1"