Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

[Arthur Heymans (Code Review)]

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Rocky Phagura, Morgan Jang, Patrick Rudolph.
Hello build bot (Jenkins), Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55098

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
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soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them

Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.

The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.

Note that with a CBnT setup APs are already halted so this code was
never run on APs! This is now also fixed.

Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/cpu.c
2 files changed, 10 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/55098/2