Change in ...coreboot[master]: mb/asrock/h81m-hds: Move GPIO header to a linked C file

[Tristan Corrick (Code Review)]

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30503

Change subject: mb/asrock/h81m-hds: Move GPIO header to a linked C file
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mb/asrock/h81m-hds: Move GPIO header to a linked C file

Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3
Signed-off-by: Tristan Corrick 
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
R src/mainboard/asrock/h81m-hds/gpio.c
M src/mainboard/asrock/h81m-hds/romstage.c
3 files changed, 2 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30503/1

diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc
index 94bd1cfe..7c1bf9e 100644
--- a/src/mainboard/asrock/h81m-hds/Makefile.inc
+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc
@@ -14,4 +14,5 @@
 ## GNU General Public License for more details.
 ##

+romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/h81m-hds/gpio.h b/src/mainboard/asrock/h81m-hds/gpio.c
similarity index 97%
rename from src/mainboard/asrock/h81m-hds/gpio.h
rename to src/mainboard/asrock/h81m-hds/gpio.c
index dde3e53..a03a52e 100644
--- a/src/mainboard/asrock/h81m-hds/gpio.h
+++ b/src/mainboard/asrock/h81m-hds/gpio.c
@@ -14,9 +14,6 @@
  * GNU General Public License for more details.
  */

-#ifndef ASROCK_H81M_HDS_GPIO_H
-#define ASROCK_H81M_HDS_GPIO_H
-
 #include <southbridge/intel/common/gpio.h>

static const struct pch_gpio_set1 pch_gpio_set1_mode = {
@@ -164,5 +161,3 @@
    	.reset		= &pch_gpio_set3_reset,
    },
 };
-
-#endif /* ASROCK_H81M_HDS_GPIO_H */
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index f3c2b3b..c6bef9f 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -20,10 +20,10 @@
 #include <cpu/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
-#include "gpio.h"

static const struct rcba_config_instruction rcba_config[] = {
    RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),