[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerG...

[Filip Brozovic (Code Review)]

Filip Brozovic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86680?usp=email )

Change subject: Revert "soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs"
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Revert "soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs"

This reverts commit 491afc3cc778ba82154f405061922da5024357c5.

Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and
'PchPciePowerGating' UPDs are also available on ADL-N.

Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b
Signed-off-by: Filip Brozovic 
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86680/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cbfd223d..d9204b4 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -922,7 +922,7 @@
    }
    s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);

-#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
+#if CONFIG(FSP_TYPE_IOT)
    /*
     * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
     * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1