Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 )
Change subject: soc/intel/alderlake: Add support for external clock buffer ......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50162/comment/a0dc0b3a_e0e7eba6 PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform.
This is mainboard specific design and nothing to do with what SoC supports. […]
@Furquan, you can looks into 2 things
1. GetPchMaxPcieClockNum function in FSP source code 2. In ADL-P any schematics that you have (RVP, Pre-CEP, CEP), i believe you will find SRCCLK_OE#7-9 derived from ADL-P PCH.
Although i'm yet to connect dots but this is what i understood, FSP is considering 10 CLKSRC for ADL-P and if we make SRCCLK8-9 Not used then its disabling those CLKSRC and device connected to RP8 (x1 slot) is unable to get detected. Hence till the time, i'm further debugging this issue, making sure those CLKSRC are not disable as we have some external device connected there and validation folks are reporting regression
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50162/comment/a34be4f9_37022690 PS1, Line 156: m_cfg->PcieClkSrcUsage[i] = 0;
Subrata, I do not understand what this change is trying to achieve. […]
i have added some answer below
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Subrata Banik (Code Review)