Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43725 )
Change subject: nb/intel/pineview/hostbridge_regs.h: Clean up registers ......................................................................
nb/intel/pineview/hostbridge_regs.h: Clean up registers
Sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/pineview/hostbridge_regs.h 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43725/1
diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h index b320b9e..506efcf 100644 --- a/src/northbridge/intel/pineview/hostbridge_regs.h +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -5,9 +5,6 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78
#define GGC 0x52 /* GMCH Graphics Control */
@@ -21,6 +18,10 @@ #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) #endif /* BOARD_DEVEN */
+#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + #define PAM0 0x90 #define PAM1 0x91 #define PAM2 0x92
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43725 )
Change subject: nb/intel/pineview/hostbridge_regs.h: Clean up registers ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43725 )
Change subject: nb/intel/pineview/hostbridge_regs.h: Clean up registers ......................................................................
nb/intel/pineview/hostbridge_regs.h: Clean up registers
Sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/pineview/hostbridge_regs.h 1 file changed, 4 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h index b320b9e..506efcf 100644 --- a/src/northbridge/intel/pineview/hostbridge_regs.h +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -5,9 +5,6 @@
#define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78
#define GGC 0x52 /* GMCH Graphics Control */
@@ -21,6 +18,10 @@ #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) #endif /* BOARD_DEVEN */
+#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + #define PAM0 0x90 #define PAM1 0x91 #define PAM2 0x92
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Georgi (Code Review)