Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86311?usp=email )
Change subject: mb/google/rauru: Reorder PCIe reset in romstage ......................................................................
mb/google/rauru: Reorder PCIe reset in romstage
Reorder the PCIe reset before mtk_dram_init to overlap the de-assert time with the DRAM initialization process.
BRANCH=rauru TEST=Build pass BUG=b:391333055
Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2 Signed-off-by: Jarried Lin jarried.lin@mediatek.corp-partner.google.com --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/86311/1
diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 7860dfd..584af61 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -47,11 +47,10 @@ clk_buf_init(); if (CONFIG(RTC)) rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); modem_power_down(); dvfs_init(); thermal_init(); - - if (CONFIG(PCI)) - mtk_pcie_deassert_perst(); }