Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30943
Change subject: hatch: disable sw sync ......................................................................
hatch: disable sw sync
Disabling software sync since EC patches haven't landed yet.
BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set
Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/bootblock/bootblock.c 3 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30943/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1fe090f..a982e8a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -28,6 +28,7 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8dd2d84..45da84f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -1,4 +1,15 @@ chip soc/intel/cannonlake + device cpu_cluster 0 on + device lapic 0 on end + end + + register "SaGv" = "3" + register "HeciEnabled" = "1" + register "VmxEnable" = "1" + register "speed_shift_enable" = "1" + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + register "dmipwroptimize" = "1"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 08a13ea..a22ca0f 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -19,6 +19,9 @@ #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/pch.h> +//#include <cpu/x86/post_code.h> +#include <console/console.h> +#include <console/post_codes.h>
#if IS_ENABLED(CONFIG_FSP_CAR) #include <FsptUpd.h> @@ -55,6 +58,7 @@ pch_early_iorange_init(); if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(0xdd); }
void bootblock_soc_init(void)
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30943
to look at the new patch set (#2).
Change subject: hatch: disable sw sync ......................................................................
hatch: disable sw sync
Disabling software sync since EC patches haven't landed yet.
BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set
Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30943/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30943 )
Change subject: hatch: disable sw sync ......................................................................
Patch Set 2: Code-Review+2
Shelley Chen has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30943 )
Change subject: hatch: disable sw sync ......................................................................
hatch: disable sw sync
Disabling software sync since EC patches haven't landed yet.
BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set
Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/30943 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1fe090f..a982e8a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -28,6 +28,7 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH
-
Duncan Laurie (Code Review) -
Shelley Chen (Code Review)