Change in coreboot[master]: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42210 )
Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ......................................................................
arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry
Picasso will use this as the entry point when resuming from S3.
BUG=b:147042464 TEST=Boot trembyle using patch train and see reboot
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ibbfa8deb99c69e59827a6c028ce4c63f74302da3 --- M src/arch/x86/bootblock_crt0.S 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42210/1
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413..e2f42e6 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,6 +10,8 @@
#include <cpu/x86/cr.h>
+.global bootblock_protected_mode_entry + .section .text
/*
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42210 )
Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42210/1/src/arch/x86/bootblock_crt0... File src/arch/x86/bootblock_crt0.S:
https://review.coreboot.org/c/coreboot/+/42210/1/src/arch/x86/bootblock_crt0... PS1, Line 41: bootblock_protected_mode_entry: So.. everything in entry16.inc is skipped. How are IDT and GDT setup?
There is also some bits in cr0 that may be set differently from normal boot path now. Code immediately below needs CR0 EM=0, but that is very likely a power-on default.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42210 )
Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ......................................................................
Patch Set 1:
The approach with S3 resume path executing code outside secured SMRAM/TSEG might get rejected altogether, so keep the bug open.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42210 )
Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42210/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42210/1//COMMIT_MSG@9 PS1, Line 9: Picasso will use this as the entry point when resuming from S3. Please summarize the bug report, as I am forbidden access.
Raul Rangel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42210 )
Change subject: arch/x86/bootblock_ctr0.S: Export bootblock_protected_mode_entry ......................................................................
Abandoned
Going to use a picasso specific entry point
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Kyösti Mälkki (Code Review) -
Paul Menzel (Code Review)
-
Raul Rangel (Code Review)