Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81877?usp=email )
Change subject: mb/intel/ptlrvp: Add PTL reference mainboard for PTLRVP-P ......................................................................
mb/intel/ptlrvp: Add PTL reference mainboard for PTLRVP-P
This adds an initial mainboard code for ptlrvp, Intel Pantherlake reference platform.
Change-Id: Ie7b623f1b2a4ce3643d85ca423cfc9463b8f848f Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- M src/mainboard/intel/lnl_dev/Kconfig M src/mainboard/intel/lnl_dev/Kconfig.name M src/mainboard/intel/lnl_dev/fw_config.c M src/mainboard/intel/lnl_dev/romstage_fsp_params.c A src/mainboard/intel/lnl_dev/variants/ptlrvp/Makefile.mk A src/mainboard/intel/lnl_dev/variants/ptlrvp/chromeos.fmd A src/mainboard/intel/lnl_dev/variants/ptlrvp/devicetree.cb A src/mainboard/intel/lnl_dev/variants/ptlrvp/early_gpio.c A src/mainboard/intel/lnl_dev/variants/ptlrvp/gpio.c A src/mainboard/intel/lnl_dev/variants/ptlrvp/memory.c 10 files changed, 552 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81877/1
diff --git a/src/mainboard/intel/lnl_dev/Kconfig b/src/mainboard/intel/lnl_dev/Kconfig index e1c4071..a3b2cfd 100644 --- a/src/mainboard/intel/lnl_dev/Kconfig +++ b/src/mainboard/intel/lnl_dev/Kconfig @@ -27,6 +27,12 @@ select FW_CONFIG_SOURCE_VPD select X2APIC_LATE_WORKAROUND
+config BOARD_INTEL_PTLRVP + def_bool n + select BOARD_INTEL_LNL_COMMON + select SOC_INTEL_PANTHERLAKE + select CONFIG_DRIVERS_UART_8250IO + config BOARD_INTEL_LNLRVP def_bool n select BOARD_INTEL_LNL_COMMON @@ -56,6 +62,7 @@ config DEVICETREE string default "variants/lnlrvp/devicetree.cb" if BOARD_INTEL_LNLRVP + default "variants/ptlrvp/devicetree.cb" if BOARD_INTEL_PTLRVP
config FMDFILE depends on VBOOT @@ -68,19 +75,23 @@ config MAINBOARD_FAMILY string default "Intel_lnlrvp" if BOARD_INTEL_LNLRVP + default "Intel_ptlrvp" if BOARD_INTEL_PTLRVP
config MAINBOARD_PART_NUMBER string default "lnlrvp" if BOARD_INTEL_LNLRVP + default "ptlrvp" if BOARD_INTEL_PTLRVP
config VARIANT_DIR string default "lnlrvp" if BOARD_INTEL_LNLRVP + default "ptlrvp" if BOARD_INTEL_PTLRVP
config GBB_HWID string depends on CHROMEOS default "LNLRVP" if BOARD_INTEL_LNLRVP + default "PTLRVP" if BOARD_INTEL_PTLRVP
config DIMM_SPD_SIZE int @@ -89,6 +100,7 @@ choice prompt "ON BOARD EC" default LNL_CHROME_EC if BOARD_INTEL_LNLRVP + default LNL_INTEL_EC if BOARD_INTEL_PTLRVP default EC_DETECT help This option allows you to select the on board EC to use. diff --git a/src/mainboard/intel/lnl_dev/Kconfig.name b/src/mainboard/intel/lnl_dev/Kconfig.name index 666a5a5..cdfe937 100644 --- a/src/mainboard/intel/lnl_dev/Kconfig.name +++ b/src/mainboard/intel/lnl_dev/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_INTEL_LNLRVP bool "Lunarlake RVP" + +config BOARD_INTEL_PTLRVP + bool "Pantherlake RVP" diff --git a/src/mainboard/intel/lnl_dev/fw_config.c b/src/mainboard/intel/lnl_dev/fw_config.c index 78e76f7..0bd14bc 100644 --- a/src/mainboard/intel/lnl_dev/fw_config.c +++ b/src/mainboard/intel/lnl_dev/fw_config.c @@ -4,6 +4,7 @@ #include <inttypes.h> #include <baseboard/gpio.h>
+#if CONFIG(SOC_INTEL_LUNARLAKE) static const struct pad_config i2s_enable_pads[] = { /* Audio: I2S0 GPP_D9: I2S_MCLK1_OUT @@ -50,6 +51,7 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF3), PAD_CFG_NF(GPP_S7, NONE, DEEP, NF3), }; +#endif
static const struct pad_config audio_disable_pads[] = { PAD_NC(GPP_S0, NONE), @@ -73,6 +75,7 @@ printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); gpio_configure_pads(audio_disable_pads, ARRAY_SIZE(audio_disable_pads)); } +#if CONFIG(SOC_INTEL_LUNARLAKE) printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get()); if (fw_config_probe(FW_CONFIG(AUDIO, LNL_ALC1019_ALC5682I_I2S)) || fw_config_probe(FW_CONFIG(AUDIO, LNL_ALC5682I_MAX9857A_I2S))) { @@ -84,5 +87,6 @@ printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (ext codec).\n"); gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); } +#endif } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/intel/lnl_dev/romstage_fsp_params.c b/src/mainboard/intel/lnl_dev/romstage_fsp_params.c index aefa8c6..07cc556 100644 --- a/src/mainboard/intel/lnl_dev/romstage_fsp_params.c +++ b/src/mainboard/intel/lnl_dev/romstage_fsp_params.c @@ -41,9 +41,6 @@ case LNLM_LP5_RVP: memcfg_init(memupd, mem_config, &lp4_lp5_spd_info, half_populated); break; - case PTLP_LP5_RVP: - memcfg_init(memupd, mem_config, &lp4_lp5_spd_info, half_populated); - break; default: die("Unknown board id = 0x%x\n", board_id); } diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/Makefile.mk b/src/mainboard/intel/lnl_dev/variants/ptlrvp/Makefile.mk new file mode 100644 index 0000000..b554782 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/Makefile.mk @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019-2020 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += early_gpio.c +ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/chromeos.fmd b/src/mainboard/intel/lnl_dev/variants/ptlrvp/chromeos.fmd new file mode 100644 index 0000000..4db6e41 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/chromeos.fmd @@ -0,0 +1,46 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL 18M { + SI_DESC 16K + SI_EC 512K + SI_GBE 8K + SI_ME + SI_ME_PAD@16M 2M + } + SI_BIOS@0x01200000 14M { + RW_SECTION_A 4M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_SECTION_B 4M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 0xFFF00 + RW_ETC(CBFS) 0x100 + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 16K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/devicetree.cb b/src/mainboard/intel/lnl_dev/variants/ptlrvp/devicetree.cb new file mode 100644 index 0000000..e3121b5 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/devicetree.cb @@ -0,0 +1,325 @@ +# UPDATEME: Current setting is for VP +# Update for PTL RVP + +fw_config + field DEBUG 0 1 + option NONE 0 + option RMT 1 + end + field AUDIO 8 10 + option NONE 0 + option ADL_MAX98373_ALC5682I_I2S 1 + end +end + +chip soc/intel/lnl_dev + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable HECI1 interface + register "HeciEnabled" = "0" + + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + + register "pch_usb_oc_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC4)" # Type-C port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC5)" # Type-C port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC6)" # Type-C port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC7)" # Type-C port4 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A con1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A con2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # FPS + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # MCF + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" # M.2 WWAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # WLAN + + register "usb2_port_reset_msg_en[0]" = "1" + register "usb2_port_reset_msg_en[1]" = "1" + register "usb2_port_reset_msg_en[2]" = "1" + register "usb2_port_reset_msg_en[3]" = "1" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A con1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A con2 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" + + register "tcss_cap_policy[0]" = "7" + register "tcss_cap_policy[1]" = "7" + register "tcss_cap_policy[2]" = "7" + register "tcss_cap_policy[3]" = "7" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # This disabled autonomous GPIO power management for early PO + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + + # RP configuration + register "pcie_rp[PCIE_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(6)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT|PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(8)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(10)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + register "pcie_rp[PCIE_RP(12)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "1" + + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoI3cMode" = "{ + [PchSerialIoIndexI3C0] = PchSerialIoPci, + [PchSerialIoIndexI3C1] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_4T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "10" + + register "cnvi_bt_audio_offload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on end + device ref ipu off end + device ref dtt off end + device ref gna off end + device ref npu on end + device ref iaa off end + + device ref heci1 on end + + device ref thc0 off end + device ref thc1 off end + + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on end + device ref tcss_dma1 on end + + device ref pcie_rp1 on end + device ref pcie_rp2 on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref pcie_rp12 on end + + device ref ish off + chip drivers/intel/ish + register "firmware_name" = ""lnlrvp_ish.bin"" + device generic 0 off end + end + end + + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth1"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + end + end + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth2"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref usb_otg off end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 off end + end + end + + device ref i2c0 off end + device ref i2c1 off end + device ref i2c2 on end + device ref i2c3 on end + device ref i2c4 on end + device ref i2c5 on end + device ref i3c on end + + device ref ufs on end + device ref uart0 on end + device ref uart1 off end + device ref uart2 off end + + device ref gspi0 on end + device ref gspi1 on end + + device ref smbus on end + device ref gbe off end + device ref hda on end + device ref soc_espi off + end + end +end diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/early_gpio.c b/src/mainboard/intel/lnl_dev/variants/ptlrvp/early_gpio.c new file mode 100644 index 0000000..cfcc42d --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/early_gpio.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <commonlib/helpers.h> +#include <soc/soc_info.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <baseboard/board_id.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config ptlprvp_early_gpio_table[] = { + /* TODO: Add GPIO configuration for RVP-P + * including UART log + */ +}; + +void variant_configure_early_gpio_pads(void) +{ + uint8_t board_id = get_board_id(); + + switch (board_id) { + case PTLP_LP5_RVP: + printk(BIOS_DEBUG, "configuring PTLP RVP early gpios\n"); + gpio_configure_pads(ptlprvp_early_gpio_table, + ARRAY_SIZE(ptlprvp_early_gpio_table)); + break; + default: + printk(BIOS_DEBUG, "bypass early gpios configuration\n"); + } +} + diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/gpio.c b/src/mainboard/intel/lnl_dev/variants/ptlrvp/gpio.c new file mode 100644 index 0000000..8357a56 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/gpio.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <commonlib/helpers.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <baseboard/board_id.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config ptlprvp_gpio_table[] = { + /* TODO: Add GPIO configuration for RVP-P*/ +}; + +void variant_configure_gpio_pads(void) +{ + uint8_t board_id = get_board_id(); + + switch (board_id) { + case PTLP_LP5_RVP: + printk(BIOS_DEBUG, "configuring PTLP RVP gpios\n"); + gpio_configure_pads(ptlprvp_gpio_table, ARRAY_SIZE(ptlprvp_gpio_table)); + break; + default: + printk(BIOS_DEBUG, "bypass gpios configuration\n"); + } +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/lnl_dev/variants/ptlrvp/memory.c b/src/mainboard/intel/lnl_dev/variants/ptlrvp/memory.c new file mode 100644 index 0000000..ea13c6d --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/ptlrvp/memory.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/romstage.h> +#include <baseboard/board_id.h> +#include <baseboard/variants.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr1 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr2 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr3 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr4 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr5 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr6 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, + .dq1 = { 8, 9, 10, 11, 12, 13, 14, 15 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = false, /* Early Command Training */ + + .LpDdrDqDqsReTraining = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + switch (board_id) { + case PTLP_LP5_RVP: + return &lp5_mem_config; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +}
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Saurabh Mishra (Code Review)