Change in coreboot[master]: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38523 )
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again.
BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38523/1
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index e7fe907..f9ae813 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -270,6 +270,10 @@ device pci 1c.0 on chip drivers/net register "customized_leds" = "0x05af" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38523 )
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Daniel Kurtz, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38523
to look at the new patch set (#2).
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again.
BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38523/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38523 )
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38523 )
Change subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix ......................................................................
mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again.
BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 45d05d09..d84b369 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -271,6 +271,10 @@ chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled.
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Edward O'Callaghan (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)