Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
Julian Schroeder has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54065 )
Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ......................................................................
amd/cezanne: adding support for the changed AMD FSP API for USB PHY
The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it.
Signed-off-by: Julian Schroeder julianmarcusschroeder@gmail.com Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 211 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3097425..3896126 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -162,4 +162,128 @@
device ref uart_0 on end # UART0
+ register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[1] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[2] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[3] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[4] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[5] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + .Usb2PhyPort[6] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + .Usb2PhyPort[7] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + + .Usb3PhyPort[0] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .Usb3PhyPort[3] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + + .ComboPhyStaticConfig[0] = 0, + .ComboPhyStaticConfig[1] = 0, + .Version_Major = 0xd, + .Version_Minor = 0x4, + .TableLength = 0x40, + .BatteryChargerEnable = 0, + .PhyP3CpmP4Support = 0, + }" + end # chip soc/amd/cezanne diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 244f2ba..630fe19 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -7,6 +7,7 @@ #include <soc/i2c.h> #include <drivers/i2c/designware/dw_i2c.h> #include <types.h> +#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; @@ -75,6 +76,7 @@ uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset;
+ struct usb_phy_config usb_phy; };
#endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ff..e316366 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -128,5 +128,7 @@ mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset;
+ memcpy(&mcfg->usb_phy, &config->usb_phy, sizeof(struct usb_phy_config) ); + fsp_fill_pcie_ddi_descriptors(mcfg); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspUsb.h b/src/vendorcode/amd/fsp/cezanne/FspUsb.h new file mode 100644 index 0000000..23ba25d --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspUsb.h @@ -0,0 +1,77 @@ +#ifndef __FSPUSB_H__ +#define __FSPUSB_H__ + +#include <FspUpd.h> + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 4 +#define USBC_COMBO_PHY_COUNT 2 + +#if 0 +struct fch_usb2_phy __attribute__ ((__packed__)) { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +}; + +struct fch_usb3_phy __attribute__ ((__packed__)) { + uint8_t TX_TERM_CTRL; ///< tx_term_ctrl + uint8_t RX_TERM_CTRL; ///< rx_term_ctrl + uint8_t TX_VBOOST_LVL_EN; ///< TX_VBOOST_LVL_EN + uint8_t TX_VBOOST_LVL; ///< TX_VBOOST_LVL +}; + +struct usb_phy_config __attribute__ ((__packed__)) { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +}; +#else +struct fch_usb2_phy { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +} __attribute__ ((__packed__)) ; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +} __attribute__ ((__packed__)) ; + +struct usb_phy_config { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +} __attribute__ ((__packed__)) ; + +#endif + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f01af85..e53f14b 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -1,6 +1,6 @@ /** @file * - * This file is automatically generated. + * This file is _NOT_ automatically generated in coreboot! * */
@@ -8,6 +8,7 @@ #define __FSPMUPD_H__
#include <FspUpd.h> +#include <FspUsb.h>
#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 #define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 @@ -79,24 +80,7 @@ /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; - /** Offset 0x044A**/ uint8_t fch_usb_version_major; - /** Offset 0x044B**/ uint8_t fch_usb_version_minor; - /** Offset 0x044C**/ uint8_t fch_usb_2_port0_phy_tune[9]; - /** Offset 0x0455**/ uint8_t fch_usb_2_port1_phy_tune[9]; - /** Offset 0x045E**/ uint8_t fch_usb_2_port2_phy_tune[9]; - /** Offset 0x0467**/ uint8_t fch_usb_2_port3_phy_tune[9]; - /** Offset 0x0470**/ uint8_t fch_usb_2_port4_phy_tune[9]; - /** Offset 0x0479**/ uint8_t fch_usb_2_port5_phy_tune[9]; - /** Offset 0x0482**/ uint8_t fch_usb_2_port6_phy_tune[9]; - /** Offset 0x048B**/ uint8_t fch_usb_2_port7_phy_tune[9]; - /** Offset 0x0494**/ uint8_t fch_usb_device_removable; - /** Offset 0x0495**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x0496**/ uint8_t fch_usb_u3_rx_det_wa_enable; - /** Offset 0x0497**/ uint8_t fch_usb_u3_rx_det_wa_portmap; - /** Offset 0x0498**/ uint8_t fch_usb_early_debug_select_enable; - /** Offset 0x0499**/ uint32_t xhci_oc_pin_select; - /** Offset 0x049D**/ uint8_t xhci0_force_gen1; - /** Offset 0x049E**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; /** Offset 0x049F**/ uint32_t gnb_ioapic_base; /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; /** Offset 0x04A4**/ uint8_t fch_ioapic_id; @@ -107,8 +91,9 @@ /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; - /** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41]; - /** Offset 0x0500**/ uint16_t UpdTerminator; + /** Offset 0x04D7**/ struct usb_phy_config usb_phy; + /** Offset 0x053B**/ uint8_t UnusedUpdSpace1[197]; + /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG;
/** Fsp M UPD Configuration
-
Julian Schroeder (Code Review)