Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add soe devicetree settings ......................................................................
mb/google/volteer: modify and add soe devicetree settings
- add sdcard_cd_gpio - remove support for PCIE WLAN to allow WWAN to enumerate as USB - mark PcieClkSrcUsage[2] as unused - add HD Audio support - set TcssXhciEn to 1 for TCSS USB3 - add acpi info for cros-ec-spi
BUG=b:148385924, b:144933687, b:148179954 TEST=emerge-volteer coreboot chromeos-bootimage, flash to ripto and verify ripto boots to kernel.
Change-Id: I998a237a4a2587554a4f84d5625da2dfca2dc56e Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 31 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39338/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424..ab50458 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -50,18 +50,15 @@ register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" + register "sdcard_cd_gpio" = "GPP_E11"
# Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1"
- # Enable WWAN PCIE 6 using clk 2 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[2]" = "5" - register "PcieClkSrcClkReq[2]" = "2" - # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality + register "PcieClkSrcUsage[2]" = "0xFF" register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[6]" = "0xFF" @@ -110,6 +107,23 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }"
+ # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # TCSS USB3 + register "TcssXhciEn" = "1" + # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" @@ -153,7 +167,7 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| GSPI1 | Fingerprint MCU + #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C1 | Touchscreen | #| I2C2 | WLAN, SAR0 | @@ -303,7 +317,7 @@ device pci 1c.2 off end # RP3 0xA0BA device pci 1c.3 off end # RP4 0xA0BB device pci 1c.4 off end # RP5 0xA0BC - device pci 1c.5 on end # WWAN RP6 0xA0BD + device pci 1c.5 off end # WWAN RP6 0xA0BD device pci 1c.6 on end # RP7 0xA0BE device pci 1c.7 on end # SD Card RP8 0xA0BF
@@ -326,7 +340,16 @@ device spi 0 on end end end # GSPI0 0xA0AA - device pci 1e.3 on end # GSPI1 0xA0AB + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" + device spi 0 on end + end # FPMCU + end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 off end # P2SB 0xA0A0
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add soe devicetree settings ......................................................................
Patch Set 1:
(1 comment)
i'd suggest splitting this patch by subsystem affected.
https://review.coreboot.org/c/coreboot/+/39338/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39338/1//COMMIT_MSG@7 PS1, Line 7: soe speling
Hello build bot (Jenkins), Furquan Shaikh, caveh jalali, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39338
to look at the new patch set (#2).
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
mb/google/volteer: modify and add some devicetree settings
- add sdcard_cd_gpio - remove support for PCIE WLAN to allow WWAN to enumerate as USB - mark PcieClkSrcUsage[2] as unused - add HD Audio support - set TcssXhciEn to 1 for TCSS USB3 - add acpi info for cros-ec-spi
BUG=b:148385924, b:144933687, b:148179954 TEST=emerge-volteer coreboot chromeos-bootimage, flash to ripto and verify ripto boots to kernel.
Change-Id: I998a237a4a2587554a4f84d5625da2dfca2dc56e Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 31 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39338/2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39338/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39338/1//COMMIT_MSG@7 PS1, Line 7: soe
speling
Done
Hello build bot (Jenkins), Furquan Shaikh, caveh jalali, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39338
to look at the new patch set (#3).
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
mb/google/volteer: modify and add some devicetree settings
- add sdcard_cd_gpio - remove support for PCIE WLAN to allow WWAN to enumerate as USB - mark PcieClkSrcUsage[2] as unused - add HD Audio support - set TcssXhciEn to 1 for TCSS USB3 - add acpi info for cros-ec-spi
BUG=b:148385924, b:144933687, b:148179954 TEST=emerge-volteer coreboot chromeos-bootimage, flash to ripto and verify ripto boots to kernel.
Change-Id: I998a237a4a2587554a4f84d5625da2dfca2dc56e Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 31 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39338/3
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
Patch Set 3:
Patch Set 1:
(1 comment)
i'd suggest splitting this patch by subsystem affected.
Done.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
Patch Set 3: Code-Review-2
Something went wrong with upload, fixing...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39338/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39338/3/src/mainboard/google/voltee... PS3, Line 53: register "sdcard_cd_gpio" = "GPP_E11" This is not correct. Not required.
https://review.coreboot.org/c/coreboot/+/39338/3/src/mainboard/google/voltee... PS3, Line 117: # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T : register "PchHdaIDispLinkTmode" = "2" : # iDisp-Link Freq 4: 96MHz, 3: 48MHz. : register "PchHdaIDispLinkFrequency" = "4" : # Not disconnected/enumerable : register "PchHdaIDispCodecDisconnect" = "0" I don't think this is correct for Volteer. We do not use IDisp. Have you verified this is really required?
Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39338 )
Change subject: mb/google/volteer: modify and add some devicetree settings ......................................................................
Abandoned
-
caveh jalali (Code Review) -
Furquan Shaikh (Code Review)
-
Nick Vaccaro (Code Review)