Change in coreboot[master]: mb/google/dedede/var/sasuke: Add USB2 PHY parameters

[shkim (Code Review)]

Attention is currently required from: SH Kim.
Hello SH Kim,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/49321

to review the following change.

Change subject: mb/google/dedede/var/sasuke: Add USB2 PHY parameters
......................................................................

mb/google/dedede/var/sasuke: Add USB2 PHY parameters

This change adds fine-tuned USB2 PHY parameters for sasuke.

BUG=176060155
TEST=Built and verified USB2 eye diagram test result

Change-Id: Id374ed238d92077ca28c1162fd9f070029ee71bd
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/dedede/variants/sasuke/overridetree.cb
1 file changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49321/1

diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
index 987e331..57cfbc7 100644
--- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb
@@ -5,7 +5,41 @@
    register "PcieClkSrcUsage[3]" = "0xff"

# USB Port Configuration
+	register "usb2_ports[0]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_28P15MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-C Port C0
+	register "usb2_ports[1]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_16P9MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_39P35MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-C Port C1
+	register "usb2_ports[2]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_16P9MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_39P35MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-A Port A0
+	register "usb2_ports[3]" = "{
+		.enable = 1,
+		.ocpin = OC_SKIP,
+		.tx_bias = USB2_BIAS_0MV,
+		.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+		.pre_emp_bias  = USB2_BIAS_11P25MV,
+		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
+	}" # Type-A Port A1
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
    register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"

# Intel Common SoC Config
    #+-------------------+---------------------------+