New patch to review for coreboot: 860e056 pcengines/apu1: Add switch between UART and GPIO modes

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10178

-gerrit

commit 860e05686ee89160a1e581df33ebe541bf1eb2b9
Author: Kyösti Mälkki 
Date:   Mon May 11 22:53:19 2015 +0300

pcengines/apu1: Add switch between UART and GPIO modes

These are alternative customer options connected to J19 header.
    We need to avoid modifying devicetree.cb, so we fix devicetree
    for the super-io device-enables at runtime instead.

Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
    Signed-off-by: Kyösti Mälkki 
---
 src/mainboard/pcengines/apu1/Kconfig       | 30 ++++++++++++++++++++++++++++++
 src/mainboard/pcengines/apu1/devicetree.cb |  5 ++++-
 src/mainboard/pcengines/apu1/mainboard.c   | 27 +++++++++++++++++++++++++++
 3 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 9409bc3..197dbc0 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -82,4 +82,34 @@ config DRIVERS_PS2_KEYBOARD
    bool
    default n

+choice
+	prompt "J19 pins 1-10"
+	default PINMUX_OFF_C
+
+config PINMUX_OFF_C
+	bool "disable"
+
+config PINMUX_GPIO0
+	bool "GPIO"
+
+config PINMUX_UART_C
+	bool "UART 0x3e8"
+
+endchoice
+
+choice
+	prompt "J19 pins 11-20"
+	default PINMUX_OFF_D
+
+config PINMUX_OFF_D
+	bool "disable"
+
+config PINMUX_GPIO1
+	bool "GPIO"
+
+config PINMUX_UART_D
+	bool "UART 0x2e8"
+
+endchoice
+
 endif # BOARD_PCENGINES_APU1
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index b98f34d..1f07a9b 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -59,16 +59,19 @@ chip northbridge/amd/agesa/family14/root_complex
    						irq 0x70 = 3
    					end
    					device pnp 2e.10 off
+							# UART C is conditionally turned on
    						io 0x60 = 0x3e8
    						irq 0x70 = 4
    					end
    					device pnp 2e.11 off
+							# UART D is conditionally turned on
    						io 0x60 = 0x2e8
    						irq 0x70 = 3
    					end
    					device pnp 2e.8 off end
    					device pnp 2e.f off end
-						device pnp 2e.7 off end
+						# GPIO0 and GPIO1 are conditionally turned on
+						device pnp 2e.007 off end
    					device pnp 2e.107 off end
    					device pnp 2e.607 off end
    					device pnp 2e.e off end
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 3b8541c..f49059d 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -33,6 +33,7 @@
 #include "SBPLATFORM.h"
 #include <southbridge/amd/cimx/sb800/pci_devs.h>
 #include <northbridge/amd/agesa/family14/pci_devs.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"

void set_pcie_reset(void);
@@ -135,6 +136,30 @@ static void pirq_setup(void)
    picr_data_ptr = mainboard_picr_data;
 }

+/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
+ * once configuration file format for SPI flash storage is complete.
+ */
+#define SIO_PORT 0x2e
+
+static void config_gpio_mux(void)
+{
+	struct device *uart, *gpio;
+
+	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+	if (uart)
+		uart->enabled = CONFIG_PINMUX_UART_C;
+	if (gpio)
+		gpio->enabled = CONFIG_PINMUX_GPIO0;
+
+	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+	if (uart)
+		uart->enabled = CONFIG_PINMUX_UART_D;
+	if (gpio)
+		gpio->enabled = CONFIG_PINMUX_GPIO1;
+}
+
 /**
  * TODO
  * SB CIMx callback
@@ -158,6 +183,8 @@ static void mainboard_enable(device_t dev)
 {
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

+	config_gpio_mux();
+
    /* Initialize the PIRQ data structures for consumption */
    pirq_setup();
 }