Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Enable USB2_P12 and USB2_P13

[Kin Wai Ng (Code Review)]

Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/25240

to review the following change.

Change subject: mainboard/intel/coffeelake_rvp: Enable USB2_P12 and USB2_P13
......................................................................

mainboard/intel/coffeelake_rvp: Enable USB2_P12 and USB2_P13

Reference to schematic on CFL-H RVP11:
Connector J2A2 to USB2_P12 and USB2_P13

Change-Id: I93c96a25b3c7cb59255105b53eab619ca09949e9
Signed-off-by: Ng Kin Wai 
---
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/25240/1

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index a6d9a6e..2db1d07 100755
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -23,6 +23,8 @@
    register "usb2_ports[7]" = "USB2_PORT_EMPTY"
    register "usb2_ports[8]" = "USB2_PORT_EMPTY"
    register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[11]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[12]" = "USB2_PORT_MID(OC0)"

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
    register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"