Change in coreboot[master]: soc/intel/xeon_sp: Set SMI lock

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51226 )

Change subject: soc/intel/xeon_sp: Set SMI lock
......................................................................

soc/intel/xeon_sp: Set SMI lock

Prevent writes to Global SMI enable as recommended by the BWG.

Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418
Signed-off-by: Marc Jones 
---
M src/soc/intel/xeon_sp/lockdown.c
1 file changed, 17 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/51226/1

diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
index 2fa53c9..0e21680 100644
--- a/src/soc/intel/xeon_sp/lockdown.c
+++ b/src/soc/intel/xeon_sp/lockdown.c
@@ -16,7 +16,19 @@
    }
 }

-static void pmc_lockdown_config(void)
+static void pmc_lock_smi(void)
+{
+	uint8_t *pmcbase;
+	uint8_t reg8;
+
+	pmcbase = pmc_mmio_regs();
+
+	reg8 = read8(pmcbase + GEN_PMCON_A);
+	reg8 |= SMI_LOCK;
+	write8(pmcbase + GEN_PMCON_A, reg8);
+}
+
+static void pmc_lockdown_config(int chipset_lockdown)
 {
    uint8_t *pmcbase;
    u32 pmsyncreg;
@@ -29,6 +41,9 @@

/* Make sure payload/OS can't trigger global reset */
    pmc_global_reset_disable_and_lock();
+
+	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
+		pmc_lock_smi();
 }

void soc_lockdown_config(int chipset_lockdown)
@@ -37,5 +52,5 @@
    lpc_lockdown_config(chipset_lockdown);

/* PMC lock down configuration */
-	pmc_lockdown_config();
+	pmc_lockdown_config(chipset_lockdown);
 }