Change in coreboot[master]: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56105 )

Change subject: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability
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vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability

Signed-off-by: Ryan Chuang 
Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index 71415d2..b761473 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -33,7 +33,7 @@
 u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733

DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = {
-    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_OFF,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
+    {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K,  VREF_CALI_ON,  CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
     {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K,  VREF_CALI_ON,   CLOSE_LOOP_MODE},  // highest freq of term group (3733) must k first.
 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
     {LP4_DDR400  /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF,  OPEN_LOOP_MODE},