Change in coreboot[master]: soc/mediatek: rtc: Use `bool` as return type

[Yidi Lin (Code Review)]

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

soc/mediatek: rtc: Use `bool` as return type

TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada
BUG=b:176307061

Signed-off-by: Yidi Lin 
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
---
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/rtc.c
M src/soc/mediatek/mt8173/include/soc/rtc.h
M src/soc/mediatek/mt8173/rtc.c
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
M src/soc/mediatek/mt8192/include/soc/rtc.h
M src/soc/mediatek/mt8192/rtc.c
8 files changed, 61 insertions(+), 58 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/49137/1

diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h
index 7ddb8df..4a86431 100644
--- a/src/soc/mediatek/common/include/soc/rtc_common.h
+++ b/src/soc/mediatek/common/include/soc/rtc_common.h
@@ -6,6 +6,7 @@
 #include <bcd.h>
 #include <console/console.h>
 #include <rtc.h>
+#include <stdbool.h>

#define RTCTAG			"[RTC]"
 #define rtc_info(fmt, arg ...)	printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \
@@ -94,14 +95,13 @@
 };

/* external API */
-int rtc_busy_wait(void);
-int rtc_write_trigger(void);
-int rtc_writeif_unlock(void);
-int rtc_xosc_write(u16 val);
-int rtc_lpen(u16 con);
-int rtc_reg_init(void);
+bool rtc_write_trigger(void);
+bool rtc_writeif_unlock(void);
+bool rtc_xosc_write(u16 val);
+bool rtc_lpen(u16 con);
+bool rtc_reg_init(void);
 void rtc_osc_init(void);
-int rtc_powerkey_init(void);
+bool rtc_powerkey_init(void);
 void rtc_boot_common(void);

#endif /* SOC_MEDIATEK_RTC_COMMON_H */
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
index 95bd13b..f36bbc5 100644
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -5,7 +5,7 @@
 #include <timer.h>

/* ensure rtc write success */
-int rtc_busy_wait(void)
+static bool rtc_busy_wait(void)
 {
    struct stopwatch sw;
    u16 bbpu;
@@ -17,30 +17,30 @@
    	/* Time > 1sec, time out and set recovery mode enable.*/
    	if (stopwatch_expired(&sw)) {
    		rtc_info("BBPU CBUSY time out !!\n");
-			return 0;
+			return false;
    	}
    } while (bbpu & RTC_BBPU_CBUSY);

-	return 1;
+	return true;
 }

-int rtc_write_trigger(void)
+bool rtc_write_trigger(void)
 {
    rtc_write(RTC_WRTGR, 1);
    return rtc_busy_wait();
 }

/* unlock rtc write interface */
-int rtc_writeif_unlock(void)
+bool rtc_writeif_unlock(void)
 {
    rtc_write(RTC_PROT, RTC_PROT_UNLOCK1);
    if (!rtc_write_trigger())
-		return 0;
+		return false;
    rtc_write(RTC_PROT, RTC_PROT_UNLOCK2);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* set rtc time */
@@ -71,20 +71,20 @@
 }

/* set rtc xosc setting */
-int rtc_xosc_write(u16 val)
+bool rtc_xosc_write(u16 val)
 {
    u16 bbpu;

rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
    if (!rtc_busy_wait())
-		return 0;
+		return false;
    rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
    if (!rtc_busy_wait())
-		return 0;
+		return false;

rtc_write(RTC_OSC32CON, val);
    if (!rtc_busy_wait())
-		return 0;
+		return false;

rtc_read(RTC_BBPU, &bbpu);
    bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
@@ -94,31 +94,31 @@
 }

/* enable lpd subroutine */
-int rtc_lpen(u16 con)
+bool rtc_lpen(u16 con)
 {
    con &= ~RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

con |= RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

con &= ~RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* initialize rtc related registers */
-int rtc_reg_init(void)
+bool rtc_reg_init(void)
 {
    u16 irqsta;

@@ -136,7 +136,7 @@
    rtc_write(RTC_DIFF, 0);
    rtc_write(RTC_CALI, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

rtc_read(RTC_IRQ_STA, &irqsta);  /* read clear */

@@ -153,7 +153,7 @@
 }

/* write powerkeys to enable rtc functions */
-int rtc_powerkey_init(void)
+bool rtc_powerkey_init(void)
 {
    rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
    rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
index bb9425f..e82d514 100644
--- a/src/soc/mediatek/mt8173/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -5,6 +5,7 @@

#include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include "mt6391.h"

diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 94ec421..d60f722 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -10,7 +10,7 @@
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))

/* initialize rtc related gpio */
-static int rtc_gpio_init(void)
+static bool rtc_gpio_init(void)
 {
    u16 con;

@@ -41,21 +41,21 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* rtc init check */
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index f7c189f..7ca054a 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -5,6 +5,7 @@

#include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
+#include <stdbool.h>

/* RTC registers */
 enum {
@@ -205,7 +206,7 @@
 /* external API */
 void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
-int rtc_gpio_init(void);
+bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 41dc5c0..e90aa9d 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -11,7 +11,7 @@
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))

/* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
    u16 bbpu, con, osc32con, sec;

@@ -22,7 +22,7 @@
    mdelay(1);
    if (!rtc_writeif_unlock()) {
    	rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_OSC32CON, &osc32con);
@@ -32,7 +32,7 @@
    	    | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
    if (!rtc_xosc_write(osc32con)) {
    	rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_CON, &con);
@@ -40,11 +40,11 @@
    rtc_read(RTC_AL_SEC, &sec);
    rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);

-	return 1;
+	return true;
 }

/* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
    u16 con;

@@ -115,7 +115,7 @@
    	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
    	if (stopwatch_expired(&sw)) {
    		rtc_info("get frequency time out !!\n");
-			return 0;
+			return false;
    	}
    } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);

@@ -143,7 +143,7 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    u16 con, sec;

@@ -152,19 +152,19 @@
    sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
    rtc_write(RTC_AL_SEC, sec);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

/* init XOSC32 to detect 32k clock stop */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_XOSC32_LPEN;
    if (!rtc_lpen(con))
-		return 0;
+		return false;

/* init EOSC32 to detect rtc low power */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_EOSC32_LPEN;
    if (!rtc_lpen(con))
-		return 0;
+		return false;

rtc_read(RTC_CON, &con);
    con &= ~RTC_CON_XOSC32_LPEN;
@@ -176,9 +176,9 @@
    sec |= RTC_LPD_OPT_EOSC_LPD;
    rtc_write(RTC_AL_SEC, sec);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

static bool rtc_hw_init(void)
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index a26f893..440c30c 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8192_RTC_H

#include <soc/pmif.h>
+#include <stdbool.h>

/* RTC registers */
 enum {
@@ -226,7 +227,7 @@
 void rtc_write(u16 addr, u16 wdata);
 void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
-int rtc_gpio_init(void);
+bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6359_dcxo_disable_unused(void);
diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c
index ffb9a5c..f978202 100644
--- a/src/soc/mediatek/mt8192/rtc.c
+++ b/src/soc/mediatek/mt8192/rtc.c
@@ -42,11 +42,11 @@
 }

/* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
    if (!rtc_writeif_unlock()) {
    	rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
    }

u16 bbpu, con, osc32con, sec;
@@ -59,18 +59,18 @@

if (!rtc_xosc_write(osc32con)) {
    	rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_CON, &con);
    rtc_read(RTC_OSC32CON, &osc32con);
    rtc_read(RTC_AL_SEC, &sec);
    rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec);
-	return 1;
+	return true;
 }

/* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
    u16 con;

@@ -135,7 +135,7 @@
    	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
    	if (stopwatch_expired(&sw)) {
    		rtc_info("get frequency time out!\n");
-			return 0;
+			return false;
    	}
    } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);

@@ -163,7 +163,7 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    u16 con, sec;

@@ -173,26 +173,26 @@
    rtc_write(RTC_AL_SEC, sec);

if (!rtc_write_trigger())
-		return 0;
+		return false;

/* init XOSC32 to detect 32k clock stop */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_XOSC32_LPEN;

if (!rtc_lpen(con))
-		return 0;
+		return false;

/* init EOSC32 to detect rtc low power */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_EOSC32_LPEN;

if (!rtc_lpen(con))
-		return 0;
+		return false;

rtc_read(RTC_CON, &con);
    rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con);

-	return 1;
+	return true;
 }

static bool rtc_hw_init(void)

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

Patch Set 1:

Hung-Te & Yu-Ping,

Please review this patch.

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

Patch Set 1:

please first fix the lint failure (clkbuf has extra lines) to get Verified+1...

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

Patch Set 4:
> Patch Set 1:
>
> please first fix the lint failure (clkbuf has extra lines) to get Verified+1...

I rebase this patch to the head of the chain.

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

Patch Set 4: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/49137/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/49137/4//COMMIT_MSG@11 
PS4, Line 11: BUG=b:176307061
Move BUG before TEST.

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49137

to look at the new patch set (#5).

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

soc/mediatek: rtc: Use `bool` as return type

BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin 
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
---
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/rtc.c
M src/soc/mediatek/mt8173/include/soc/rtc.h
M src/soc/mediatek/mt8173/rtc.c
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
M src/soc/mediatek/mt8192/include/soc/rtc.h
M src/soc/mediatek/mt8192/rtc.c
8 files changed, 61 insertions(+), 58 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/49137/5

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/49137/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/49137/4//COMMIT_MSG@11 
PS4, Line 11: BUG=b:176307061
> Move BUG before TEST.

Done

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49137

to look at the new patch set (#6).

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

soc/mediatek: rtc: Use `bool` as return type

BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin 
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
---
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/rtc.c
M src/soc/mediatek/mt8173/include/soc/rtc.h
M src/soc/mediatek/mt8173/rtc.c
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
M src/soc/mediatek/mt8192/include/soc/rtc.h
M src/soc/mediatek/mt8192/rtc.c
8 files changed, 61 insertions(+), 58 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/49137/6

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49137 )

Change subject: soc/mediatek: rtc: Use `bool` as return type
......................................................................

soc/mediatek: rtc: Use `bool` as return type

BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin 
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/rtc.c
M src/soc/mediatek/mt8173/include/soc/rtc.h
M src/soc/mediatek/mt8173/rtc.c
M src/soc/mediatek/mt8183/include/soc/rtc.h
M src/soc/mediatek/mt8183/rtc.c
M src/soc/mediatek/mt8192/include/soc/rtc.h
M src/soc/mediatek/mt8192/rtc.c
8 files changed, 61 insertions(+), 58 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h
index 7ddb8df..4a86431 100644
--- a/src/soc/mediatek/common/include/soc/rtc_common.h
+++ b/src/soc/mediatek/common/include/soc/rtc_common.h
@@ -6,6 +6,7 @@
 #include <bcd.h>
 #include <console/console.h>
 #include <rtc.h>
+#include <stdbool.h>

#define RTCTAG			"[RTC]"
 #define rtc_info(fmt, arg ...)	printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \
@@ -94,14 +95,13 @@
 };

/* external API */
-int rtc_busy_wait(void);
-int rtc_write_trigger(void);
-int rtc_writeif_unlock(void);
-int rtc_xosc_write(u16 val);
-int rtc_lpen(u16 con);
-int rtc_reg_init(void);
+bool rtc_write_trigger(void);
+bool rtc_writeif_unlock(void);
+bool rtc_xosc_write(u16 val);
+bool rtc_lpen(u16 con);
+bool rtc_reg_init(void);
 void rtc_osc_init(void);
-int rtc_powerkey_init(void);
+bool rtc_powerkey_init(void);
 void rtc_boot_common(void);

#endif /* SOC_MEDIATEK_RTC_COMMON_H */
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
index 95bd13b..f36bbc5 100644
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -5,7 +5,7 @@
 #include <timer.h>

/* ensure rtc write success */
-int rtc_busy_wait(void)
+static bool rtc_busy_wait(void)
 {
    struct stopwatch sw;
    u16 bbpu;
@@ -17,30 +17,30 @@
    	/* Time > 1sec, time out and set recovery mode enable.*/
    	if (stopwatch_expired(&sw)) {
    		rtc_info("BBPU CBUSY time out !!\n");
-			return 0;
+			return false;
    	}
    } while (bbpu & RTC_BBPU_CBUSY);

-	return 1;
+	return true;
 }

-int rtc_write_trigger(void)
+bool rtc_write_trigger(void)
 {
    rtc_write(RTC_WRTGR, 1);
    return rtc_busy_wait();
 }

/* unlock rtc write interface */
-int rtc_writeif_unlock(void)
+bool rtc_writeif_unlock(void)
 {
    rtc_write(RTC_PROT, RTC_PROT_UNLOCK1);
    if (!rtc_write_trigger())
-		return 0;
+		return false;
    rtc_write(RTC_PROT, RTC_PROT_UNLOCK2);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* set rtc time */
@@ -71,20 +71,20 @@
 }

/* set rtc xosc setting */
-int rtc_xosc_write(u16 val)
+bool rtc_xosc_write(u16 val)
 {
    u16 bbpu;

rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
    if (!rtc_busy_wait())
-		return 0;
+		return false;
    rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
    if (!rtc_busy_wait())
-		return 0;
+		return false;

rtc_write(RTC_OSC32CON, val);
    if (!rtc_busy_wait())
-		return 0;
+		return false;

rtc_read(RTC_BBPU, &bbpu);
    bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
@@ -94,31 +94,31 @@
 }

/* enable lpd subroutine */
-int rtc_lpen(u16 con)
+bool rtc_lpen(u16 con)
 {
    con &= ~RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

con |= RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

con &= ~RTC_CON_LPRST;
    rtc_write(RTC_CON, con);

if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* initialize rtc related registers */
-int rtc_reg_init(void)
+bool rtc_reg_init(void)
 {
    u16 irqsta;

@@ -136,7 +136,7 @@
    rtc_write(RTC_DIFF, 0);
    rtc_write(RTC_CALI, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

rtc_read(RTC_IRQ_STA, &irqsta);  /* read clear */

@@ -153,7 +153,7 @@
 }

/* write powerkeys to enable rtc functions */
-int rtc_powerkey_init(void)
+bool rtc_powerkey_init(void)
 {
    rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
    rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
index bb9425f..e82d514 100644
--- a/src/soc/mediatek/mt8173/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -5,6 +5,7 @@

#include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
+#include <stdbool.h>
 #include <stdint.h>
 #include "mt6391.h"

diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 94ec421..d60f722 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -10,7 +10,7 @@
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))

/* initialize rtc related gpio */
-static int rtc_gpio_init(void)
+static bool rtc_gpio_init(void)
 {
    u16 con;

@@ -41,21 +41,21 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

/* rtc init check */
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index f7c189f..7ca054a 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -5,6 +5,7 @@

#include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
+#include <stdbool.h>

/* RTC registers */
 enum {
@@ -205,7 +206,7 @@
 /* external API */
 void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
-int rtc_gpio_init(void);
+bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 41dc5c0..e90aa9d 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -11,7 +11,7 @@
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))

/* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
    u16 bbpu, con, osc32con, sec;

@@ -22,7 +22,7 @@
    mdelay(1);
    if (!rtc_writeif_unlock()) {
    	rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_OSC32CON, &osc32con);
@@ -32,7 +32,7 @@
    	    | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
    if (!rtc_xosc_write(osc32con)) {
    	rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_CON, &con);
@@ -40,11 +40,11 @@
    rtc_read(RTC_AL_SEC, &sec);
    rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);

-	return 1;
+	return true;
 }

/* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
    u16 con;

@@ -115,7 +115,7 @@
    	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
    	if (stopwatch_expired(&sw)) {
    		rtc_info("get frequency time out !!\n");
-			return 0;
+			return false;
    	}
    } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);

@@ -143,7 +143,7 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    u16 con, sec;

@@ -152,19 +152,19 @@
    sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
    rtc_write(RTC_AL_SEC, sec);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

/* init XOSC32 to detect 32k clock stop */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_XOSC32_LPEN;
    if (!rtc_lpen(con))
-		return 0;
+		return false;

/* init EOSC32 to detect rtc low power */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_EOSC32_LPEN;
    if (!rtc_lpen(con))
-		return 0;
+		return false;

rtc_read(RTC_CON, &con);
    con &= ~RTC_CON_XOSC32_LPEN;
@@ -176,9 +176,9 @@
    sec |= RTC_LPD_OPT_EOSC_LPD;
    rtc_write(RTC_AL_SEC, sec);
    if (!rtc_write_trigger())
-		return 0;
+		return false;

-	return 1;
+	return true;
 }

static bool rtc_hw_init(void)
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index 15e0d2d..491aeab 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8192_RTC_H

#include <soc/pmif.h>
+#include <stdbool.h>

/* RTC registers */
 enum {
@@ -224,7 +225,7 @@
 void rtc_write(u16 addr, u16 wdata);
 void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
-int rtc_gpio_init(void);
+bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6359_dcxo_disable_unused(void);
diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c
index 8615873..d966cab 100644
--- a/src/soc/mediatek/mt8192/rtc.c
+++ b/src/soc/mediatek/mt8192/rtc.c
@@ -41,11 +41,11 @@
 }

/* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
    if (!rtc_writeif_unlock()) {
    	rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
    }

u16 bbpu, con, osc32con, sec;
@@ -58,18 +58,18 @@

if (!rtc_xosc_write(osc32con)) {
    	rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
    }

rtc_read(RTC_CON, &con);
    rtc_read(RTC_OSC32CON, &osc32con);
    rtc_read(RTC_AL_SEC, &sec);
    rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec);
-	return 1;
+	return true;
 }

/* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
    u16 con;

@@ -134,7 +134,7 @@
    	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
    	if (stopwatch_expired(&sw)) {
    		rtc_info("get frequency time out!\n");
-			return 0;
+			return false;
    	}
    } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);

@@ -162,7 +162,7 @@
 }

/* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
    u16 con, sec;

@@ -172,26 +172,26 @@
    rtc_write(RTC_AL_SEC, sec);

if (!rtc_write_trigger())
-		return 0;
+		return false;

/* init XOSC32 to detect 32k clock stop */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_XOSC32_LPEN;

if (!rtc_lpen(con))
-		return 0;
+		return false;

/* init EOSC32 to detect rtc low power */
    rtc_read(RTC_CON, &con);
    con |= RTC_CON_EOSC32_LPEN;

if (!rtc_lpen(con))
-		return 0;
+		return false;

rtc_read(RTC_CON, &con);
    rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con);

-	return 1;
+	return true;
 }

static bool rtc_hw_init(void)