[S] Change in coreboot[main]: [TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISA...

[Tyler Wang (Code Review)]

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82720?usp=email )

Change subject: [TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN is set
......................................................................

[TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN is set

This patch add function `mainboard_check_lid_state()` to check GBB
flag VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN before transfer setting to
LidStatus. If the flag is set, LidStatus will be "1" even lid closed,
otherwise LidStatus will be set by real lid status.

BUG=b:333982806
TEST=none

Change-Id: Ieef5a4268baf17fb6b1bb4941d2d71befa7febb1
Signed-off-by: Tyler Wang 
---
M src/mainboard/google/brya/mainboard.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/include/soc/ramstage.h
3 files changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/82720/1

diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 07aa4b5..ca81062 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -3,12 +3,14 @@
 #include <acpi/acpigen.h>
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <bootmode.h>
 #include <device/device.h>
 #include <drivers/tpm/cr50.h>
 #include <drivers/wwan/fm/chip.h>
 #include <ec/ec.h>
 #include <fw_config.h>
 #include <security/tpm/tss.h>
+#include <security/vboot/vboot_common.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <stdio.h>
@@ -132,6 +134,14 @@
    	acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF"));
 }

+UINT8 mainboard_check_lid_state(void)
+{
+	if (vboot_is_disable_lid_close_shutdown())
+		return CONFIG(RUN_FSP_GOP);
+	else
+		return CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+}
+
 static void mainboard_generate_mpts(void)
 {
    const struct device *wwan = DEV_PTR(rp6_wwan);
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index ff5c83c..562191f 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -634,6 +634,11 @@
    	s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
 }

+__weak UINT8 mainboard_check_lid_state(void)
+{
+	return CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+}
+
 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
@@ -642,7 +647,7 @@

/* Check if IGD is present and fill Graphics init param accordingly */
    s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
-	s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
+	s_cfg->LidStatus = mainboard_check_lid_state();
    s_cfg->PavpEnable = CONFIG(PAVP);
 }

diff --git a/src/soc/intel/alderlake/include/soc/ramstage.h b/src/soc/intel/alderlake/include/soc/ramstage.h
index e655198..9d30b0e 100644
--- a/src/soc/intel/alderlake/include/soc/ramstage.h
+++ b/src/soc/intel/alderlake/include/soc/ramstage.h
@@ -10,5 +10,6 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config);
 void soc_init_pre_device(void *chip_info);
+UINT8 mainboard_check_lid_state(void);

#endif