[S] Change in coreboot[main]: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82264?usp=email )

Change subject: cpu/x86/mtrr: Add soc_fill_uc_holes_in_physical_address_space
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Patch Set 8:

(1 comment)

File src/cpu/x86/mtrr/mtrr.c:

https://review.coreboot.org/c/coreboot/+/82264/comment/1e045bc6_d8c128e5?usp... :
PS3, Line 203: soc_update_physical_address_space
> Yes, exactly. […]

There seem to be no specification when it comes to MTRRs.
In theory you could not only fill UC holes, but grow the memory ranges to optimize the MTRRs. Growing is possible when not limited by another region. It should allow to minimize MTRR usage as well as you could align base and size to the next power of two.