Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email )
Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ......................................................................
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
Xeon-SP FSP2.4 contains changes in IIO stack descriptors which will further impacts the way of coreboot's creating domains. This patch separates the codes as preparation for FSP2.4 based platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_common.c A src/soc/intel/xeon_sp/chip_fsp20.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 4 files changed, 194 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81312/1
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 1f96bb7..a9af93b 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -15,6 +15,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += chip_fsp20.c +ramstage-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += chip_fsp20.c +ramstage-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += chip_fsp20.c smm-y += smihandler.c pmutil.c postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index ef504d7..44981f8 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -12,19 +12,6 @@ #include <soc/util.h> #include <stdlib.h>
-static const STACK_RES *domain_to_stack_res(const struct device *dev) -{ - assert(dev->path.type == DEVICE_PATH_DOMAIN); - const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain - }; - - const IIO_UDS *hob = get_iio_uds(); - assert(hob != NULL); - - return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; -} - /** * Find all device of a given vendor and type for the specified socket. * The function iterates over all PCI domains of the specified socket @@ -189,81 +176,7 @@ return dn.stack; }
-void iio_pci_domain_read_resources(struct device *dev) -{ - struct resource *res; - const STACK_RES *sr = domain_to_stack_res(dev); - - if (!sr) - return; - - int index = 0; - - if (is_domain0(dev)) { - /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ - res = new_resource(dev, index++); - res->base = 0; - res->size = 0x1000; - res->limit = 0xfff; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceIoBase; - res->limit = sr->PciResourceIoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem32Base; - res->limit = sr->PciResourceMem32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } - - if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem64Base; - res->limit = sr->PciResourceMem64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } -} - -/* - * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, - * all the bus numbers on the IIO stack can be used for this bridge - */ -static struct device_operations iio_pcie_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -/* - * Used by UBOX stacks. Those contain multiple PCI host bridges, each having - * only one bus with UBOX devices. UBOX devices have no resources. - */ -static struct device_operations ubox_pcie_domain_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -static void soc_create_domains(const union xeon_domain_path dp, struct bus *upstream, +void soc_create_domains(const union xeon_domain_path dp, struct bus *upstream, int bus_base, int bus_limit, const char *type, struct device_operations *ops) { @@ -283,91 +196,6 @@ bus->max_subordinate = bus_limit; }
- -static void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, - const STACK_RES *sr) -{ - soc_create_domains(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops); -} - -/* - * On the first Xeon-SP generations there are no separate UBOX stacks, - * and the UBOX devices reside on the first and second IIO. Starting - * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. - */ -static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, - const STACK_RES *sr) -{ - /* Only expect 2 UBOX buses here */ - assert(sr->BusBase + 1 == sr->BusLimit); - - soc_create_domains(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, - &ubox_pcie_domain_ops); - soc_create_domains(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, - &ubox_pcie_domain_ops); -} - -#if CONFIG(SOC_INTEL_HAS_CXL) -void iio_cxl_domain_read_resources(struct device *dev) -{ - struct resource *res; - const STACK_RES *sr = domain_to_stack_res(dev); - - if (!sr) - return; - - int index = 0; - - if (sr->IoBase < sr->PciResourceIoBase) { - res = new_resource(dev, index++); - res->base = sr->IoBase; - res->limit = sr->PciResourceIoBase - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } - - if (sr->Mmio32Base < sr->PciResourceMem32Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio32Base; - res->limit = sr->PciResourceMem32Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } - - if (sr->Mmio64Base < sr->PciResourceMem64Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio64Base; - res->limit = sr->PciResourceMem64Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } -} - -static struct device_operations iio_cxl_domain_ops = { - .read_resources = iio_cxl_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_host_bridge_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = soc_acpi_name, - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = pci_domain_fill_ssdt, -#endif -}; - -void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, - const STACK_RES *sr) -{ - assert(sr->BusBase + 1 <= sr->BusLimit); - /* 1st domain contains PCIe RCiEPs */ - soc_create_domains(dp, bus, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops); - /* 2nd domain contains CXL 1.1 end-points */ - soc_create_domains(dp, bus, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, - &iio_cxl_domain_ops); -} -#endif //CONFIG(SOC_INTEL_HAS_CXL) - /* Attach stack as domains */ void attach_iio_stacks(void) { diff --git a/src/soc/intel/xeon_sp/chip_fsp20.c b/src/soc/intel/xeon_sp/chip_fsp20.c new file mode 100644 index 0000000..d453475 --- /dev/null +++ b/src/soc/intel/xeon_sp/chip_fsp20.c @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen_pci.h> +#include <assert.h> +#include <console/console.h> +#include <device/pci.h> +#include <intelblocks/acpi.h> +#include <post.h> +#include <soc/acpi.h> +#include <soc/chip_common.h> +#include <soc/soc_util.h> +#include <soc/util.h> +#include <stdlib.h> + +static const STACK_RES *domain_to_stack_res(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_DOMAIN); + const union xeon_domain_path dn = { + .domain_path = dev->path.domain.domain + }; + + const IIO_UDS *hob = get_iio_uds(); + assert(hob != NULL); + + return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; +} + + +void iio_pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + + if (!sr) + return; + + int index = 0; + + if (is_domain0(dev)) { + /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ + res = new_resource(dev, index++); + res->base = 0; + res->size = 0x1000; + res->limit = 0xfff; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceIoBase; + res->limit = sr->PciResourceIoLimit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem32Base; + res->limit = sr->PciResourceMem32Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } + + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { + res = new_resource(dev, index++); + res->base = sr->PciResourceMem64Base; + res->limit = sr->PciResourceMem64Limit; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } +} + +/* + * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, + * all the bus numbers on the IIO stack can be used for this bridge + */ +static struct device_operations iio_pcie_domain_ops = { + .read_resources = iio_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr) +{ + soc_create_domains(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, + &iio_pcie_domain_ops); +} + +/* + * Used by UBOX stacks. Those contain multiple PCI host bridges, each having + * only one bus with UBOX devices. UBOX devices have no resources. + */ +static struct device_operations ubox_pcie_domain_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +/* + * On the first Xeon-SP generations there are no separate UBOX stacks, + * and the UBOX devices reside on the first and second IIO. Starting + * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. + */ +void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr) +{ + /* Only expect 2 UBOX buses here */ + assert(sr->BusBase + 1 == sr->BusLimit); + + soc_create_domains(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, + &ubox_pcie_domain_ops); + soc_create_domains(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, + &ubox_pcie_domain_ops); +} + +#if CONFIG(SOC_INTEL_HAS_CXL) +void iio_cxl_domain_read_resources(struct device *dev) +{ + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + + if (!sr) + return; + + int index = 0; + + if (sr->IoBase < sr->PciResourceIoBase) { + res = new_resource(dev, index++); + res->base = sr->IoBase; + res->limit = sr->PciResourceIoBase - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio32Base < sr->PciResourceMem32Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio32Base; + res->limit = sr->PciResourceMem32Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio64Base < sr->PciResourceMem64Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio64Base; + res->limit = sr->PciResourceMem64Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } +} + +static struct device_operations iio_cxl_domain_ops = { + .read_resources = iio_cxl_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt = pci_domain_fill_ssdt, +#endif +}; + +void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, + const STACK_RES *sr) +{ + assert(sr->BusBase + 1 <= sr->BusLimit); + /* 1st domain contains PCIe RCiEPs */ + soc_create_domains(dp, bus, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, + &iio_pcie_domain_ops); + /* 2nd domain contains CXL 1.1 end-points */ + soc_create_domains(dp, bus, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, + &iio_cxl_domain_ops); +} +#endif //CONFIG(SOC_INTEL_HAS_CXL) \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index fab8166..95d30ca 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -53,8 +53,13 @@ void iio_cxl_domain_read_resources(struct device *dev); void attach_iio_stacks(void);
+void soc_create_domains(const union xeon_domain_path dp, struct bus *upstream, + int bus_base, int bus_limit, const char *type, + struct device_operations *ops); void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr); +void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr); +void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr); int soc_add_dram_resources(struct device *dev, int start_index);
struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device);
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Shuo Liu (Code Review)