Change in coreboot[master]: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46461 )

Change subject: soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
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soc/intel/skl: replace conditional on dt option reading CPUID for CPPC

Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.

Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F

Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461
Reviewed-by: Nico Huber 
Reviewed-by:  Felix Singer 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/acpi.c
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
   Felix Singer: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 275e77d..637092b 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -35,6 +35,8 @@

#include "chip.h"

+#define  CPUID_6_EAX_ISST	(1 << 7)
+
 /*
  * List of suported C-states in this processor.
  */
@@ -379,7 +381,7 @@
    printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
           numcpus, cores_per_package);

-	if (config->speed_shift_enable) {
+	if (cpuid_eax(6) & CPUID_6_EAX_ISST) {
    	struct cppc_config cppc_config;
    	cpu_init_cppc_config(&cppc_config, 2 /* version 2 */);
    	acpigen_write_CPPC_package(&cppc_config);
@@ -405,7 +407,7 @@
    					cores_per_package);
    		}

-			if (config->speed_shift_enable)
+			if (cpuid_eax(6) & CPUID_6_EAX_ISST)
    			acpigen_write_CPPC_method();

acpigen_pop_len();