Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54338 )
Change subject: mb/asus/p8z77: Add P8Z77-V as a variant of P8x7x ......................................................................
mb/asus/p8z77: Add P8Z77-V as a variant of P8x7x
Tested: - PS/2 keyboard with SeaBIOS - Integrated NIC - S3 Suspend to RAM - USB2 on rear - USB3 (Z77's and Asmedia's works) - Integrated SATA - CPU Temp sensors (tested PSensor on GNU/Linux) - TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) - Native raminit - Integrated graphics with both libgfxinit (VGA/DVI-D/HDMI tested and working) - PCIe GPU in PCIe-16x/8x slots (tested using an S3 Matrix) - Debug output from serial port - Atheros AR9485 adapted with Wi-Fi Go! Adapter - Default PCIe config
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 --- A Documentation/mainboard/asus/p8z77-v.jpg A Documentation/mainboard/asus/p8z77-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/Kconfig.name A src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c A src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt A src/mainboard/asus/p8x7x/variants/z77-v/data.vbt A src/mainboard/asus/p8x7x/variants/z77-v/early_init.c A src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads A src/mainboard/asus/p8x7x/variants/z77-v/gpio.c A src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c A src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c A src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb 14 files changed, 514 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/54338/1
diff --git a/Documentation/mainboard/asus/p8z77-v.jpg b/Documentation/mainboard/asus/p8z77-v.jpg new file mode 100644 index 0000000..00f3c68 --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-v.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md new file mode 100644 index 0000000..0f4b649 --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-v.md @@ -0,0 +1,120 @@ +# ASUS P8Z77-V + +This page describes how to run coreboot on the [ASUS P8Z77-V] + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash IC is located between the black and white PCI Express x16 slots (circled): + + +### Internal programming + +The main SPI flash cannot be written because Asus disables BIOSWE and +enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses. +An external programmer is required. You must flash standalone, +flashing in-circuit doesn't work. The flash chip is socketed, so it's +easy to remove and reflash. + +## Working + +- PS/2 keyboard with SeaBIOS + +- Integrated NIC + +- S3 Suspend to RAM + +- USB2 on rear + +- USB3 (Z77's and Asmedia's works) + +- Integrated SATA + +- CPU Temp sensors (tested PSensor on GNU/Linux) + +- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12) + +- Native raminit + +- Integrated graphics with both libgfxinit (VGA/DVI-D/HDMI tested and working) + +- PCIe GPU in PCIe-16x/8x slots (tested using an S3 Matrix) + +- Debug output from serial port + +- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter + +- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below + for other potential options) + +## Untested + +- EHCI debugging +- S/PDIF audio +- PS/2 mouse + +## Not working + +- PCIEX_1_2 (expected under default PCIe config) +- Other PCIe configs (see below) + +## PCIe config +On asus vendor firmware, other than the default config already supported here, +there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2 +and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2, +with onboard ASM1061 disabled". + +Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but +also needs to config GPIOs in the superio chip different than the default config +in this board's override tree. + +Configuring PCIe Port 4 to PCIEX_1_2 needs to config GPIOs in the superio chip +different than the default config. + +I have tried a lot, but sadly I am unable to produce the same result as the vendor +firmware. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3307271..06286d4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -22,6 +22,7 @@ - [P8H61-M LX](asus/p8h61-m_lx.md) - [P8H61-M Pro](asus/p8h61-m_pro.md) - [P8Z77-M Pro](asus/p8z77-m_pro.md) +- [P8Z77-V](asus/p8z77-v.md)
## Cavium
diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig index 163e337..c758ff7 100644 --- a/src/mainboard/asus/p8x7x/Kconfig +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only
-if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 +if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 || BOARD_ASUS_P8Z77_V
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,7 +11,7 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 - select MAINBOARD_HAS_LPC_TPM if BOARD_ASUS_P8Z77_M_PRO + select MAINBOARD_HAS_LPC_TPM if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select MAINBOARD_HAS_LIBGFXINIT @@ -19,7 +19,8 @@ select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT # for ASM1061 eSATA - select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO + select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_ASUS_P8Z77_V
config MAINBOARD_DIR string @@ -29,14 +30,16 @@ string default "z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 + default "z77-v" if BOARD_ASUS_P8Z77_V
config MAINBOARD_PART_NUMBER string default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 + default "P8Z77-V" if BOARD_ASUS_P8Z77_V
config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-endif # BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 +endif # BOARD_ASUS_P8Z77_M_PRO || BOARD_ASUS_P8Z77_V_LX2 || BOARD_ASUS_P8Z77_V diff --git a/src/mainboard/asus/p8x7x/Kconfig.name b/src/mainboard/asus/p8x7x/Kconfig.name index 2777435..fca045a 100644 --- a/src/mainboard/asus/p8x7x/Kconfig.name +++ b/src/mainboard/asus/p8x7x/Kconfig.name @@ -5,3 +5,6 @@
config BOARD_ASUS_P8Z77_V_LX2 bool "P8Z77-V LX2" + +config BOARD_ASUS_P8Z77_V + bool "P8Z77-V" diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c b/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c new file mode 100644 index 0000000..8f4f83b --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt b/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt new file mode 100644 index 0000000..135878b --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/board_info.txt @@ -0,0 +1,3 @@ +Board name: ASUS P8Z77-V +Board URL: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/ +Release year: 2013 diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt b/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt new file mode 100644 index 0000000..37fa165 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c new file mode 100644 index 0000000..825da64 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/early_init.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> +#include <option.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 0, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads b/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads new file mode 100644 index 0000000..83a87be --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + Others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c b/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c new file mode 100644 index 0000000..5d5e4e7 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c b/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c new file mode 100644 index 0000000..e431593 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x104384fb, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384fb), + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c b/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c new file mode 100644 index 0000000..ac992f6 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable +}; diff --git a/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb b/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb new file mode 100644 index 0000000..2a3fec7 --- /dev/null +++ b/src/mainboard/asus/p8x7x/variants/z77-v/overridetree.cb @@ -0,0 +1,57 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0x0 on + device pci 01.1 on end # PCIEX_16_2 + chip southbridge/intel/bd82x6x + register "pcie_port_coalesce" = "1" + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x4) + device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1 + device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2 + device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge + device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go! + device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # PS2 KBC + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.7 off end # GPIOs 6-8 + device pnp 2e.8 off end # WDT1 GPIO 0-1 + device pnp 2e.108 on end # GPIO0-1 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + drq 0xe0 = 0xdf + end + device pnp 2e.309 on end # GPIO3 + device pnp 2e.509 on # GPIO5 + drq 0xf4 = 0xfc + end + device pnp 2e.a on # ACPI + drq 0xe3 = 0x04 # Thermal shutdown event issued + drq 0xe7 = 0x11 # Enable 3VSBS to power RAM on S3 + drq 0xf2 = 0x5d # Enable PME + end + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.f on # Push-pull/Open-drain + drq 0xe4 = 0xfc # GP5 PP + drq 0xe6 = 0x7f # GP7 PP + end + end + chip drivers/pc80/tpm + device pnp c31.0 on end # TPM + end + end + end + end +end
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Bill XIE (Code Review)