Change in coreboot[master]: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m ......................................................................
mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index bc2d5ce..92c877f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -6,228 +6,1061 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), -/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), -/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), -/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), -/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), -/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), -/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), -/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), -/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), -/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), -/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), -/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), -/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), -/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), -/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), -/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), -/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), -/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), -/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), -/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), -/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), -/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), -/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), -/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), -/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), -/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), -/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), -/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), -/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), -/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), -/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), -/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), -/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), -/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), -/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), -/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), + /* GPP_A0 - RCIN# */ + /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A7 - PIRQA# */ + /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A11 - PME# */ + /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A12 - GPIO */ + /* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_A13 - SUSWARN# */ + /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A14 - SUS_STAT# */ + /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A15 - SUS_ACK# */ + /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A16 - CLKOUT_48 */ + /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A17 - GPIO */ + /* PAD_NC(GPP_A17, NONE), */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A18 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_A19 - RESERVED */ + + /* GPP_A20 - GPIO */ + /* PAD_NC(GPP_A20, NONE), */ + _PAD_CFG_STRUCT(GPP_A20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A21 - GPIO */ + /* PAD_NC(GPP_A21, NONE), */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A22 - GPIO */ + /* PAD_NC(GPP_A22, NONE), */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A23 - GPIO */ + /* PAD_NC(GPP_A23, NONE), */ + _PAD_CFG_STRUCT(GPP_A23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B0 - GPIO */ + /* PAD_CFG_GPO(GPP_B0, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B1 - GPIO */ + /* PAD_CFG_GPO(GPP_B1, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B2 - GPIO */ + /* PAD_NC(GPP_B2, NONE), */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B3 - GPIO */ + /* PAD_NC(GPP_B3, NONE), */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B4 - GPIO */ + /* PAD_NC(GPP_B4, NONE), */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B5 - GPIO */ + /* PAD_NC(GPP_B5, NONE), */ + _PAD_CFG_STRUCT(GPP_B5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B6 - GPIO */ + /* PAD_NC(GPP_B6, NONE), */ + _PAD_CFG_STRUCT(GPP_B6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B7 - GPIO */ + /* PAD_NC(GPP_B7, NONE), */ + _PAD_CFG_STRUCT(GPP_B7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B8 - GPIO */ + /* PAD_NC(GPP_B8, NONE), */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B9 - GPIO */ + /* PAD_NC(GPP_B9, NONE), */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B10 - GPIO */ + /* PAD_NC(GPP_B10, NONE), */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B11 - GPIO */ + /* PAD_CFG_GPO(GPP_B11, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_B12 - SLP_S0# */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B13 - PLTRST# */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B14 - SPKR */ + /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B15 - GPIO */ + /* PAD_NC(GPP_B15, NONE), */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B16 - GPIO */ + /* PAD_NC(GPP_B16, NONE), */ + _PAD_CFG_STRUCT(GPP_B16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B17 - GPIO */ + /* PAD_NC(GPP_B17, NONE), */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B18 - GPIO */ + /* PAD_NC(GPP_B18, NONE), */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B19 - GPIO */ + /* PAD_NC(GPP_B19, NONE), */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B20 - GPIO */ + /* PAD_CFG_GPO(GPP_B20, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B21 - GPIO */ + /* PAD_NC(GPP_B21, NONE), */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B22 - GPIO */ + /* PAD_NC(GPP_B22, NONE), */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B23 - PCHHOT# */ + /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C0 - RESERVED */ + + /* GPP_C1 - RESERVED */ + + /* GPP_C2 - GPIO */ + /* PAD_NC(GPP_C2, NONE), */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C3 - RESERVED */ + + /* GPP_C4 - RESERVED */ + + /* GPP_C5 - GPIO */ + /* PAD_CFG_GPO(GPP_C5, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_C6 - RESERVED */ + + /* GPP_C7 - RESERVED */ + + /* GPP_C8 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_C9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_C10 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_C11 - GPIO */ + /* PAD_NC(GPP_C11, NONE), */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C12 - GPIO */ + /* PAD_NC(GPP_C12, NONE), */ + _PAD_CFG_STRUCT(GPP_C12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C13 - GPIO */ + /* PAD_NC(GPP_C13, NONE), */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C14 - GPIO */ + /* PAD_NC(GPP_C14, NONE), */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C15 - GPIO */ + /* PAD_NC(GPP_C15, NONE), */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C16 - GPIO */ + /* PAD_NC(GPP_C16, NONE), */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C17 - GPIO */ + /* PAD_NC(GPP_C17, NONE), */ + _PAD_CFG_STRUCT(GPP_C17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C18 - GPIO */ + /* PAD_NC(GPP_C18, NONE), */ + _PAD_CFG_STRUCT(GPP_C18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C19 - GPIO */ + /* PAD_NC(GPP_C19, NONE), */ + _PAD_CFG_STRUCT(GPP_C19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C20 - GPIO */ + /* PAD_NC(GPP_C20, NONE), */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C21 - GPIO */ + /* PAD_NC(GPP_C21, NONE), */ + _PAD_CFG_STRUCT(GPP_C21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C22 - GPIO */ + /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_C23 - GPIO */ + /* PAD_NC(GPP_C23, NONE), */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D0 - GPIO */ + /* PAD_NC(GPP_D0, NONE), */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D1 - GPIO */ + /* PAD_CFG_GPO(GPP_D1, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_D1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D2 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_D3 - GPIO */ + /* PAD_NC(GPP_D3, NONE), */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D4 - GPIO */ + /* PAD_CFG_GPO(GPP_D4, 0, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_D5 - GPIO */ + /* PAD_NC(GPP_D5, NONE), */ + _PAD_CFG_STRUCT(GPP_D5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D6 - GPIO */ + /* PAD_NC(GPP_D6, NONE), */ + _PAD_CFG_STRUCT(GPP_D6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D7 - GPIO */ + /* PAD_NC(GPP_D7, NONE), */ + _PAD_CFG_STRUCT(GPP_D7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D8 - GPIO */ + /* PAD_NC(GPP_D8, NONE), */ + _PAD_CFG_STRUCT(GPP_D8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D9 - GPIO */ + /* PAD_NC(GPP_D9, NONE), */ + _PAD_CFG_STRUCT(GPP_D9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D10 - GPIO */ + /* PAD_NC(GPP_D10, NONE), */ + _PAD_CFG_STRUCT(GPP_D10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D11 - GPIO */ + /* PAD_NC(GPP_D11, NONE), */ + _PAD_CFG_STRUCT(GPP_D11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D12 - GPIO */ + /* PAD_NC(GPP_D12, NONE), */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D13 - GPIO */ + /* PAD_NC(GPP_D13, NONE), */ + _PAD_CFG_STRUCT(GPP_D13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D14 - GPIO */ + /* PAD_NC(GPP_D14, NONE), */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D15 - GPIO */ + /* PAD_NC(GPP_D15, NONE), */ + _PAD_CFG_STRUCT(GPP_D15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D16 - GPIO */ + /* PAD_NC(GPP_D16, NONE), */ + _PAD_CFG_STRUCT(GPP_D16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D17 - GPIO */ + /* PAD_NC(GPP_D17, NONE), */ + _PAD_CFG_STRUCT(GPP_D17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D18 - GPIO */ + /* PAD_CFG_GPO(GPP_D18, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D19 - GPIO */ + /* PAD_CFG_GPO(GPP_D19, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D20 - GPIO */ + /* PAD_NC(GPP_D20, NONE), */ + _PAD_CFG_STRUCT(GPP_D20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D21 - GPIO */ + /* PAD_CFG_GPO(GPP_D21, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_D21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_D22 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_D22, + PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_D23 - GPIO */ + /* PAD_NC(GPP_D23, NONE), */ + _PAD_CFG_STRUCT(GPP_D23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E0 - SATAXPCIE0 */ + /* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_E1 - GPIO */ + /* PAD_NC(GPP_E1, NONE), */ + _PAD_CFG_STRUCT(GPP_E1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E2 - GPIO */ + /* PAD_NC(GPP_E2, NONE), */ + _PAD_CFG_STRUCT(GPP_E2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E3 - GPIO */ + /* PAD_NC(GPP_E3, NONE), */ + _PAD_CFG_STRUCT(GPP_E3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E4 - GPIO */ + /* PAD_NC(GPP_E4, NONE), */ + _PAD_CFG_STRUCT(GPP_E4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E5 - GPIO */ + /* PAD_NC(GPP_E5, NONE), */ + _PAD_CFG_STRUCT(GPP_E5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E6 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_E6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_E7 - GPIO */ + /* PAD_NC(GPP_E7, NONE), */ + _PAD_CFG_STRUCT(GPP_E7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E8 - SATA_LED# */ + /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E9 - USB_OC0# */ + /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E10 - USB_OC1# */ + /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E11 - USB_OC2# */ + /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E12 - USB_OC3# */ + /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F0 - GPIO */ + /* PAD_NC(GPP_F0, NONE), */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F1 - GPIO */ + /* PAD_NC(GPP_F1, NONE), */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F2 - GPIO */ + /* PAD_NC(GPP_F2, NONE), */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F3 - GPIO */ + /* PAD_NC(GPP_F3, NONE), */ + _PAD_CFG_STRUCT(GPP_F3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F4 - GPIO */ + /* PAD_NC(GPP_F4, NONE), */ + _PAD_CFG_STRUCT(GPP_F4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F5 - GPIO */ + /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F6 - GPIO */ + /* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F7 - GPIO */ + /* PAD_CFG_GPO(GPP_F7, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F8 - GPIO */ + /* PAD_CFG_GPO(GPP_F8, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F10 - SATA_SCLOCK */ + /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F11 - SATA_SLOAD */ + /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F12 - SATA_SDATAOUT1 */ + /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F13 - SATA_SDATAOUT2 */ + /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F14 - GPIO */ + /* PAD_NC(GPP_F14, NONE), */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F15 - USB_OC4# */ + /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F16 - USB_OC5# */ + /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F17 - GPIO */ + /* PAD_NC(GPP_F17, NONE), */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F18 - GPIO */ + /* PAD_NC(GPP_F18, NONE), */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F19 - GPIO */ + /* PAD_NC(GPP_F19, NONE), */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F20 - GPIO */ + /* PAD_NC(GPP_F20, NONE), */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F21 - GPIO */ + /* PAD_NC(GPP_F21, NONE), */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F22 - GPIO */ + /* PAD_NC(GPP_F22, NONE), */ + _PAD_CFG_STRUCT(GPP_F22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F23 - GPIO */ + /* PAD_CFG_GPO(GPP_F23, 0, PWROK), */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_G0 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G2 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G3 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G4 - GPIO */ + /* PAD_NC(GPP_G4, NONE), */ + _PAD_CFG_STRUCT(GPP_G4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G5 - GPIO */ + /* PAD_NC(GPP_G5, NONE), */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G6 - GPIO */ + /* PAD_NC(GPP_G6, NONE), */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G7 - GPIO */ + /* PAD_NC(GPP_G7, NONE), */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G8 - GPIO */ + /* PAD_NC(GPP_G8, NONE), */ + _PAD_CFG_STRUCT(GPP_G8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G9 - GPIO */ + /* PAD_NC(GPP_G9, NONE), */ + _PAD_CFG_STRUCT(GPP_G9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G10 - GPIO */ + /* PAD_NC(GPP_G10, NONE), */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G11 - GPIO */ + /* PAD_NC(GPP_G11, NONE), */ + _PAD_CFG_STRUCT(GPP_G11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G12 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G13 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G14 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G15 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G16 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G17 - GPIO */ + /* PAD_NC(GPP_G17, NONE), */ + _PAD_CFG_STRUCT(GPP_G17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G18 - NMI# */ + /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G18, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G19 - SMI# */ + /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G19, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G20 - GPIO */ + /* PAD_NC(GPP_G20, NONE), */ + _PAD_CFG_STRUCT(GPP_G20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G21 - GPIO */ + /* PAD_NC(GPP_G21, NONE), */ + _PAD_CFG_STRUCT(GPP_G21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G22 - GPIO */ + /* PAD_NC(GPP_G22, NONE), */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G23 - GPIO */ + /* PAD_NC(GPP_G23, NONE), */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H0 - GPIO */ + /* PAD_CFG_GPO(GPP_H0, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + + /* GPP_H2 - GPIO */ + /* PAD_CFG_GPO(GPP_H2, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H3 - SRCCLKREQ9# */ + /* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + + /* GPP_H4 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + + /* GPP_H5 - GPIO */ + /* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H6 - GPIO */ + /* PAD_CFG_GPO(GPP_H6, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H7 - GPIO */ + /* PAD_CFG_GPO(GPP_H7, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H8 - GPIO */ + /* PAD_CFG_GPO(GPP_H8, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H9 - GPIO */ + /* PAD_CFG_GPO(GPP_H9, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H10 - SML2CLK */ + /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H11 - SML2DATA */ + /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H12 - GPIO */ + /* PAD_NC(GPP_H12, NONE), */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H13 - SML3CLK */ + /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H14 - SML3DATA */ + /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H15 - GPIO */ + /* PAD_NC(GPP_H15, NONE), */ + _PAD_CFG_STRUCT(GPP_H15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H16 - SML4CLK */ + /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H17 - SML4DATA */ + /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H17, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H18 - GPIO */ + /* PAD_NC(GPP_H18, NONE), */ + _PAD_CFG_STRUCT(GPP_H18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H19 - GPIO */ + /* PAD_CFG_GPO(GPP_H19, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H20 - GPIO */ + /* PAD_CFG_GPO(GPP_H20, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H21 - GPIO */ + /* PAD_CFG_GPO(GPP_H21, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H22 - GPIO */ + /* PAD_CFG_GPO(GPP_H22, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H23 - GPIO */ + /* PAD_CFG_GPO(GPP_H23, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPD0 - GPIO */ + /* PAD_NC(GPD0, NONE), */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD1 - GPIO */ + /* PAD_NC(GPD1, NONE), */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD2 - LAN_WAKE# */ + /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD2, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPD3 - PWRBTN# */ + /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD3, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPD4 - SLP_S3# */ + /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD4, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD5 - SLP_S4# */ + /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD5, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD6 - SLP_A# */ + /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD6, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD7 - GPIO */ + /* PAD_NC(GPD7, NONE), */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPD8 - SUSCLK */ + /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD9 - GPIO */ + /* PAD_NC(GPD9, NONE), */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD10 - GPIO */ + /* PAD_NC(GPD10, NONE), */ + _PAD_CFG_STRUCT(GPD10, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD11 - GPIO */ + /* PAD_NC(GPD11, NONE), */ + _PAD_CFG_STRUCT(GPD11, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I0 - DDPB_HPD0 */ + /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I1 - DDPC_HPD1 */ + /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I2 - DDPD_HPD2 */ + /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I3 - DDPE_HPD3 */ + /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I4 - GPIO */ + /* PAD_NC(GPP_I4, NONE), */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I5 - DDPB_CTRLCLK */ + /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I6 - DDPB_CTRLDATA */ + /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I7 - DDPC_CTRLCLK */ + /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I8 - DDPC_CTRLDATA */ + /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I9 - DDPD_CTRLCLK */ + /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I10 - DDPD_CTRLDATA */ + /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), };
/*** XXX TODO XXX */ /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* LPC */ + /* LPC */
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), };
#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 0c47a9d..34960bf 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -6,251 +6,1306 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { /* GPIO Group GPP_A */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_A0 - RCIN# */ + /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A7 - PIRQA# */ + /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A11 - PME# */ + /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A12 - GPIO */ + /* PAD_NC(GPP_A12, NONE), */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A14 - SUS_STAT# */ + /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A15 - SUS_ACK# */ + /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A16 - CLKOUT_48 */ + /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A17 - GPIO */ + /* PAD_NC(GPP_A17, NONE), */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A18 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A19 - ISH_GP1 (RESERVED) */ + + /* GPP_A20 - GPIO */ + /* PAD_NC(GPP_A20, NONE), */ + _PAD_CFG_STRUCT(GPP_A20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A21 - GPIO */ + /* PAD_NC(GPP_A21, NONE), */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A22 - GPIO */ + /* PAD_NC(GPP_A22, NONE), */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A23 - GPIO */ + /* PAD_NC(GPP_A23, NONE), */ + _PAD_CFG_STRUCT(GPP_A23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_B */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ - _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPP_B0 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B1 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B2 - GPIO */ + /* PAD_NC(GPP_B2, NONE), */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B3 - GPIO */ + /* PAD_NC(GPP_B3, NONE), */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B4 - GPIO */ + /* PAD_NC(GPP_B4, NONE), */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B5 - GPIO */ + /* PAD_NC(GPP_B5, NONE), */ + _PAD_CFG_STRUCT(GPP_B5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B6 - GPIO */ + /* PAD_NC(GPP_B6, NONE), */ + _PAD_CFG_STRUCT(GPP_B6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B7 - GPIO */ + /* PAD_NC(GPP_B7, NONE), */ + _PAD_CFG_STRUCT(GPP_B7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B8 - GPIO */ + /* PAD_NC(GPP_B8, NONE), */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B9 - GPIO */ + /* PAD_NC(GPP_B9, NONE), */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B10 - GPIO */ + /* PAD_NC(GPP_B10, NONE), */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B11 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B12 - SLP_S0# */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B13 - PLTRST# */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B14 - SPKR */ + /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B15 - GPIO */ + /* PAD_NC(GPP_B15, NONE), */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B16 - GPIO */ + /* PAD_NC(GPP_B16, NONE), */ + _PAD_CFG_STRUCT(GPP_B16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B17 - GPIO */ + /* PAD_NC(GPP_B17, NONE), */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B18 - GPIO */ + /* PAD_NC(GPP_B18, NONE), */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B19 - GPIO */ + /* PAD_NC(GPP_B19, NONE), */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B20 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B21 - GPIO */ + /* PAD_NC(GPP_B21, NONE), */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B22 - GPIO */ + /* PAD_NC(GPP_B22, NONE), */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B23 - PCHHOT# */ + /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_C */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ - //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ - //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ - //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ - _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPP_C0 - SMBCLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C0, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C1 - SMBDATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C1, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C2 - GPIO */ + /* PAD_NC(GPP_C2, NONE), */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C3 - SML0CLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C3, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C4 - SML0DATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C4, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C5 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C6 - SML1CLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C6, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C7 - SML1DATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C7, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C8 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C10 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C11 - GPIO */ + /* PAD_NC(GPP_C11, NONE), */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C12 - GPIO */ + /* PAD_NC(GPP_C12, NONE), */ + _PAD_CFG_STRUCT(GPP_C12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C13 - GPIO */ + /* PAD_NC(GPP_C13, NONE), */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C14 - GPIO */ + /* PAD_NC(GPP_C14, NONE), */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C15 - GPIO */ + /* PAD_NC(GPP_C15, NONE), */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C16 - GPIO */ + /* PAD_NC(GPP_C16, NONE), */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C17 - GPIO */ + /* PAD_NC(GPP_C17, NONE), */ + _PAD_CFG_STRUCT(GPP_C17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C18 - GPIO */ + /* PAD_NC(GPP_C18, NONE), */ + _PAD_CFG_STRUCT(GPP_C18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C19 - GPIO */ + /* PAD_NC(GPP_C19, NONE), */ + _PAD_CFG_STRUCT(GPP_C19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C20 - GPIO */ + /* PAD_NC(GPP_C20, NONE), */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C21 - GPIO */ + /* PAD_NC(GPP_C21, NONE), */ + _PAD_CFG_STRUCT(GPP_C21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C22 - GPIO */ + /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU) | PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C23 - GPIO */ + /* PAD_NC(GPP_C23, NONE), */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_D */ - _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_D0 - GPIO */ + /* PAD_NC(GPP_D0, NONE), */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D1 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_D1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D2 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU)), + + /* GPP_D3 - GPIO */ + /* PAD_NC(GPP_D3, NONE), */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D4 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D5 - GPIO */ + /* PAD_NC(GPP_D5, NONE), */ + _PAD_CFG_STRUCT(GPP_D5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D6 - GPIO */ + /* PAD_NC(GPP_D6, NONE), */ + _PAD_CFG_STRUCT(GPP_D6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D7 - GPIO */ + /* PAD_NC(GPP_D7, NONE), */ + _PAD_CFG_STRUCT(GPP_D7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D8 - GPIO */ + /* PAD_NC(GPP_D8, NONE), */ + _PAD_CFG_STRUCT(GPP_D8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D9 - GPIO */ + /* PAD_NC(GPP_D9, NONE), */ + _PAD_CFG_STRUCT(GPP_D9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D10 - GPIO */ + /* PAD_NC(GPP_D10, NONE), */ + _PAD_CFG_STRUCT(GPP_D10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D11 - GPIO */ + /* PAD_NC(GPP_D11, NONE), */ + _PAD_CFG_STRUCT(GPP_D11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D12 - GPIO */ + /* PAD_NC(GPP_D12, NONE), */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D13 - GPIO */ + /* PAD_NC(GPP_D13, NONE), */ + _PAD_CFG_STRUCT(GPP_D13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D14 - GPIO */ + /* PAD_NC(GPP_D14, NONE), */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D15 - GPIO */ + /* PAD_NC(GPP_D15, NONE), */ + _PAD_CFG_STRUCT(GPP_D15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D16 - GPIO */ + /* PAD_NC(GPP_D16, NONE), */ + _PAD_CFG_STRUCT(GPP_D16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D17 - GPIO */ + /* PAD_NC(GPP_D17, NONE), */ + _PAD_CFG_STRUCT(GPP_D17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D18 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D19 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D20 - GPIO */ + /* PAD_NC(GPP_D20, NONE), */ + _PAD_CFG_STRUCT(GPP_D20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D21 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_D21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D22 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_D22, + PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D23 - GPIO */ + /* PAD_NC(GPP_D23, NONE), */ + _PAD_CFG_STRUCT(GPP_D23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_E */ - _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPP_E0 - GPIO */ + /* PAD_NC(GPP_E0, NONE), */ + _PAD_CFG_STRUCT(GPP_E0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E1 - GPIO */ + /* PAD_NC(GPP_E1, NONE), */ + _PAD_CFG_STRUCT(GPP_E1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E2 - GPIO */ + /* PAD_NC(GPP_E2, NONE), */ + _PAD_CFG_STRUCT(GPP_E2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E3 - GPIO */ + /* PAD_NC(GPP_E3, NONE), */ + _PAD_CFG_STRUCT(GPP_E3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E4 - GPIO */ + /* PAD_NC(GPP_E4, NONE), */ + _PAD_CFG_STRUCT(GPP_E4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E5 - GPIO */ + /* PAD_NC(GPP_E5, NONE), */ + _PAD_CFG_STRUCT(GPP_E5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E6 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_E6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU)), + + /* GPP_E7 - GPIO */ + /* PAD_NC(GPP_E7, NONE), */ + _PAD_CFG_STRUCT(GPP_E7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E8 - SATA_LED# */ + /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E9 - USB_OC0# */ + /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E10 - USB_OC1# */ + /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E11 - USB_OC2# */ + /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E12 - USB_OC3# */ + /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_F */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */ + + /* GPP_F0 - GPIO */ + /* PAD_NC(GPP_F0, NONE), */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F1 - GPIO */ + /* PAD_NC(GPP_F1, NONE), */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F2 - GPIO */ + /* PAD_NC(GPP_F2, NONE), */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F3 - GPIO */ + /* PAD_NC(GPP_F3, NONE), */ + _PAD_CFG_STRUCT(GPP_F3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F4 - GPIO */ + /* PAD_NC(GPP_F4, NONE), */ + _PAD_CFG_STRUCT(GPP_F4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F5 - GPIO */ + /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F6 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F7 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F8 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F10 - SATA_SCLOCK */ + /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F11 - SATA_SLOAD */ + /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F12 - SATA_SDATAOUT1 */ + /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F13 - SATA_SDATAOUT2 */ + /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F14 - GPIO */ + /* PAD_NC(GPP_F14, NONE), */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F15 - USB_OC4# */ + /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F16 - USB_OC5# */ + /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F17 - GPIO */ + /* PAD_NC(GPP_F17, NONE), */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F18 - GPIO */ + /* PAD_NC(GPP_F18, NONE), */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F19 - GPIO */ + /* PAD_NC(GPP_F19, NONE), */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F20 - GPIO */ + /* PAD_NC(GPP_F20, NONE), */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F21 - GPIO */ + /* PAD_NC(GPP_F21, NONE), */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F22 - GPIO */ + /* PAD_NC(GPP_F22, NONE), */ + _PAD_CFG_STRUCT(GPP_F22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F23 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | (3 << 30) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_G */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ - _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_G0 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G2 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G3 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G4 - GPIO */ + /* PAD_NC(GPP_G4, NONE), */ + _PAD_CFG_STRUCT(GPP_G4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G5 - GPIO */ + /* PAD_NC(GPP_G5, NONE), */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G6 - GPIO */ + /* PAD_NC(GPP_G6, NONE), */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G7 - GPIO */ + /* PAD_NC(GPP_G7, NONE), */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G8 - GPIO */ + /* PAD_NC(GPP_G8, NONE), */ + _PAD_CFG_STRUCT(GPP_G8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G9 - GPIO */ + /* PAD_NC(GPP_G9, NONE), */ + _PAD_CFG_STRUCT(GPP_G9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G10 - GPIO */ + /* PAD_NC(GPP_G10, NONE), */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G11 - GPIO */ + /* PAD_NC(GPP_G11, NONE), */ + _PAD_CFG_STRUCT(GPP_G11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G12 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G13 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G14 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G15 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G16 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G17 - GPIO */ + /* PAD_NC(GPP_G17, NONE), */ + _PAD_CFG_STRUCT(GPP_G17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G18 - NMI# */ + /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G18, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G19 - SMI# */ + /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G19, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G20 - GPIO */ + /* PAD_NC(GPP_G20, NONE), */ + _PAD_CFG_STRUCT(GPP_G20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G21 - GPIO */ + /* PAD_NC(GPP_G21, NONE), */ + _PAD_CFG_STRUCT(GPP_G21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G22 - GPIO */ + /* PAD_NC(GPP_G22, NONE), */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G23 - GPIO */ + /* PAD_NC(GPP_G23, NONE), */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_H */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ - _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ - _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ - _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ - _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPP_H0 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H2 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H3 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H4 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H5 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H6 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H7 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H8 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H9 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H10 - SML2CLK */ + /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H11 - SML2DATA */ + /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H12 - GPIO */ + /* PAD_NC(GPP_H12, NONE), */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H13 - SML3CLK */ + /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H14 - SML3DATA */ + /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H15 - GPIO */ + /* PAD_NC(GPP_H15, NONE), */ + _PAD_CFG_STRUCT(GPP_H15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H16 - SML4CLK */ + /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H17 - SML4DATA */ + /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H17, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H18 - GPIO */ + /* PAD_NC(GPP_H18, NONE), */ + _PAD_CFG_STRUCT(GPP_H18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H19 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H20 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H21 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H22 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H23 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_I */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ - _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPP_I0 - DDPB_HPD0 */ + /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I1 - DDPC_HPD1 */ + /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I2 - DDPD_HPD2 */ + /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I3 - DDPE_HPD3 */ + /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I4 - GPIO */ + /* PAD_NC(GPP_I4, NONE), */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I5 - DDPB_CTRLCLK */ + /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I6 - DDPB_CTRLDATA */ + /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I7 - DDPC_CTRLCLK */ + /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I8 - DDPC_CTRLDATA */ + /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I9 - DDPD_CTRLCLK */ + /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I10 - DDPD_CTRLDATA */ + /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPD */ - _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ - _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ - _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ - _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ - _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ - _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ - _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ + + /* GPD0 - GPIO */ + /* PAD_NC(GPD0, NONE), */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD1 - GPIO */ + /* PAD_NC(GPD1, NONE), */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD2 - LAN_WAKE# */ + /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD2, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD3 - PWRBTN# */ + /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD3, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD4 - SLP_S3# */ + /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD4, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD5 - SLP_S4# */ + /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD5, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD6 - SLP_A# */ + /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD6, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD7 - GPIO */ + /* PAD_NC(GPD7, NONE), */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD8 - SUSCLK */ + /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD9 - GPIO */ + /* PAD_NC(GPD9, NONE), */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD10 - GPIO */ + /* PAD_NC(GPD10, NONE), */ + _PAD_CFG_STRUCT(GPD10, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD11 - GPIO */ + /* PAD_NC(GPD11, NONE), */ + _PAD_CFG_STRUCT(GPD11, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), };
/* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* GPIO Group GPP_A */ /* LPC */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* Serial interrupt */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), };
#endif /* _GPIO_X11SSM_F_H */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m ......................................................................
Patch Set 2:
(62 comments)
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/2/src/mainboard/supermicro/x1... PS2, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42916
to look at the new patch set (#3).
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m ......................................................................
mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m ......................................................................
Patch Set 3:
(62 comments)
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: mb/supermicro/x11-lga1151: 1/5 Rewrite pad config using intelp2m ......................................................................
Patch Set 3:
(62 comments)
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/3/src/mainboard/supermicro/x1... PS3, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42916
to look at the new patch set (#4).
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
supermicro/x11-lga1151/gpio: 1/5 Decode raw register values
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/5 Decode raw register values CB:42917 - 2/5 Exclude fields for PAD_CFG CB:42918 - 3/5 Fixes some field macro CB:35679 - 3/4 Convert field macros to PAD_CFG CB:42919 - 5/5 Remap reset sources
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42916
to look at the new patch set (#5).
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
supermicro/x11-lga1151/gpio: 1/5 Decode raw register values
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/5 Decode raw register values CB:42917 - 2/5 Exclude fields for PAD_CFG CB:42918 - 3/5 Fixes some field macro CB:35679 - 3/4 Convert field macros to PAD_CFG CB:42919 - 5/5 Remap reset sources
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 5:
(62 comments)
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/5/src/mainboard/supermicro/x1... PS5, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 6:
(62 comments)
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 580: PWROK I'm not sure about the reset values here. Did you change this by hand here to split it off to CB:42919? I've already taken care of the reset mapping in the raw version and now I'm really confused 😄
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 6:
(1 comment)
Thanks for the review
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 580: PWROK
I'm not sure about the reset values here. […]
No, I decided to set 0, since 3h = Reserved. It seems to me that it is better not to use the reserved value here. I would like to know your opinion about this.
If you took into account remapping in gpio.h, then I will abandon the last patch (CB:42919).
I will make changes to intel2m to cancel remapping reset sources if we convert the gpio.h file.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 6:
(1 comment)
I'm unsure if splitting the changes is really worth it or if the conversion can be done in a single commit
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 580: PWROK
No, I decided to set 0, since 3h = Reserved. […]
You have to think it the other way round. What is specified in gpio.h currently (0x3) is the logical value (RSMRST), which gets converted by the table rst_map_com2 in src/soc/intel/skylake/gpio.c to 0x0 (chipset value).
That means, the original chipset value was 0x0 but I had to convert it to the logical value (see commit 71b1ed8f7).
So my suggestion would be: instead of doing the conversion in step 5/5 just do it here and abandon 5/5
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/5 Decode raw register values ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 580: PWROK
You have to think it the other way round. What is specified in gpio. […]
Ah, I understood. Thanks. I agree with you.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42916
to look at the new patch set (#7).
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
supermicro/x11-lga1151/gpio: 1/4 Decode raw register values
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -adv -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Tested with BUILD_TIMELESS=1
This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/7
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/6/src/mainboard/supermicro/x1... PS6, Line 580: PWROK
Ah, I understood. Thanks. […]
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 7:
(63 comments)
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 465: PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/7/src/mainboard/supermicro/x1... PS7, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 8:
(63 comments)
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 465: PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/8/src/mainboard/supermicro/x1... PS8, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 8: Code-Review+2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 9:
(63 comments)
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 465: PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/9/src/mainboard/supermicro/x1... PS9, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 10:
(63 comments)
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 465: PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/10/src/mainboard/supermicro/x... PS10, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Hello build bot (Jenkins), Nico Huber, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42916
to look at the new patch set (#12).
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
supermicro/x11-lga1151/gpio: 1/4 Decode raw register values
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical.
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42916/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
Patch Set 13:
(63 comments)
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 14: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 19: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 29: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 49: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 69: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 74: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 89: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 151: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 156: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 161: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 166: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 171: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 176: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 181: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 231: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 273: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 283: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 343: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 364: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 445: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 450: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 465: PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 475: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 505: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 521: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 526: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 531: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 536: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 566: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 571: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 576: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 581: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 586: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 616: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 621: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 671: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 676: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 731: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 786: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 796: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 801: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 806: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 811: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 816: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 821: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 826: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 831: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 836: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 846: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 851: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 861: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 866: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 876: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 881: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 886: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 891: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 896: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 1023: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 1033: PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 436: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 462: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 632: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), line over 96 characters
https://review.coreboot.org/c/coreboot/+/42916/13/src/mainboard/supermicro/x... PS13, Line 706: PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), line over 96 characters
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42916 )
Change subject: supermicro/x11-lga1151/gpio: 1/4 Decode raw register values ......................................................................
supermicro/x11-lga1151/gpio: 1/4 Decode raw register values
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical.
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 2,319 insertions(+), 431 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index bc2d5ce..d0df0bd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -6,228 +6,1061 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), -/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), -/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), -/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), -/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0xc4000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), -/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), -/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), -/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), -/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), -/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), -/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), -/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), -/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), -/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), -/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), -/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), -/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), -/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), -/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), -/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), -/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), -/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), -/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), -/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), -/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), -/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), -/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), -/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), -/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), -/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), -/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), -/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), -/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), -/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), -/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), -/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), + /* GPP_A0 - RCIN# */ + /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A7 - PIRQA# */ + /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A11 - PME# */ + /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A12 - GPIO */ + /* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_A13 - SUSWARN# */ + /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A14 - SUS_STAT# */ + /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A15 - SUS_ACK# */ + /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A16 - CLKOUT_48 */ + /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A17 - GPIO */ + /* PAD_NC(GPP_A17, NONE), */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A18 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_A19 - RESERVED */ + + /* GPP_A20 - GPIO */ + /* PAD_NC(GPP_A20, NONE), */ + _PAD_CFG_STRUCT(GPP_A20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A21 - GPIO */ + /* PAD_NC(GPP_A21, NONE), */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A22 - GPIO */ + /* PAD_NC(GPP_A22, NONE), */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A23 - GPIO */ + /* PAD_NC(GPP_A23, NONE), */ + _PAD_CFG_STRUCT(GPP_A23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B0 - GPIO */ + /* PAD_CFG_GPO(GPP_B0, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B1 - GPIO */ + /* PAD_CFG_GPO(GPP_B1, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B2 - GPIO */ + /* PAD_NC(GPP_B2, NONE), */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B3 - GPIO */ + /* PAD_NC(GPP_B3, NONE), */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B4 - GPIO */ + /* PAD_NC(GPP_B4, NONE), */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B5 - GPIO */ + /* PAD_NC(GPP_B5, NONE), */ + _PAD_CFG_STRUCT(GPP_B5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B6 - GPIO */ + /* PAD_NC(GPP_B6, NONE), */ + _PAD_CFG_STRUCT(GPP_B6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B7 - GPIO */ + /* PAD_NC(GPP_B7, NONE), */ + _PAD_CFG_STRUCT(GPP_B7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B8 - GPIO */ + /* PAD_NC(GPP_B8, NONE), */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B9 - GPIO */ + /* PAD_NC(GPP_B9, NONE), */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B10 - GPIO */ + /* PAD_NC(GPP_B10, NONE), */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPP_B11 - GPIO */ + /* PAD_CFG_GPO(GPP_B11, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_B12 - SLP_S0# */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B13 - PLTRST# */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B14 - SPKR */ + /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B15 - GPIO */ + /* PAD_NC(GPP_B15, NONE), */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B16 - GPIO */ + /* PAD_NC(GPP_B16, NONE), */ + _PAD_CFG_STRUCT(GPP_B16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B17 - GPIO */ + /* PAD_NC(GPP_B17, NONE), */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B18 - GPIO */ + /* PAD_NC(GPP_B18, NONE), */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B19 - GPIO */ + /* PAD_NC(GPP_B19, NONE), */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B20 - GPIO */ + /* PAD_CFG_GPO(GPP_B20, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_B21 - GPIO */ + /* PAD_NC(GPP_B21, NONE), */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B22 - GPIO */ + /* PAD_NC(GPP_B22, NONE), */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_B23 - PCHHOT# */ + /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C0 - RESERVED */ + + /* GPP_C1 - RESERVED */ + + /* GPP_C2 - GPIO */ + /* PAD_NC(GPP_C2, NONE), */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C3 - RESERVED */ + + /* GPP_C4 - RESERVED */ + + /* GPP_C5 - GPIO */ + /* PAD_CFG_GPO(GPP_C5, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_C6 - RESERVED */ + + /* GPP_C7 - RESERVED */ + + /* GPP_C8 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_C9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_C10 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_C11 - GPIO */ + /* PAD_NC(GPP_C11, NONE), */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C12 - GPIO */ + /* PAD_NC(GPP_C12, NONE), */ + _PAD_CFG_STRUCT(GPP_C12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C13 - GPIO */ + /* PAD_NC(GPP_C13, NONE), */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C14 - GPIO */ + /* PAD_NC(GPP_C14, NONE), */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C15 - GPIO */ + /* PAD_NC(GPP_C15, NONE), */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C16 - GPIO */ + /* PAD_NC(GPP_C16, NONE), */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C17 - GPIO */ + /* PAD_NC(GPP_C17, NONE), */ + _PAD_CFG_STRUCT(GPP_C17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C18 - GPIO */ + /* PAD_NC(GPP_C18, NONE), */ + _PAD_CFG_STRUCT(GPP_C18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C19 - GPIO */ + /* PAD_NC(GPP_C19, NONE), */ + _PAD_CFG_STRUCT(GPP_C19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C20 - GPIO */ + /* PAD_NC(GPP_C20, NONE), */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C21 - GPIO */ + /* PAD_NC(GPP_C21, NONE), */ + _PAD_CFG_STRUCT(GPP_C21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_C22 - GPIO */ + /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_C23 - GPIO */ + /* PAD_NC(GPP_C23, NONE), */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D0 - GPIO */ + /* PAD_NC(GPP_D0, NONE), */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D1 - GPIO */ + /* PAD_CFG_GPO(GPP_D1, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_D1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D2 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_D3 - GPIO */ + /* PAD_NC(GPP_D3, NONE), */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D4 - GPIO */ + /* PAD_CFG_GPO(GPP_D4, 0, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_D5 - GPIO */ + /* PAD_NC(GPP_D5, NONE), */ + _PAD_CFG_STRUCT(GPP_D5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D6 - GPIO */ + /* PAD_NC(GPP_D6, NONE), */ + _PAD_CFG_STRUCT(GPP_D6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D7 - GPIO */ + /* PAD_NC(GPP_D7, NONE), */ + _PAD_CFG_STRUCT(GPP_D7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D8 - GPIO */ + /* PAD_NC(GPP_D8, NONE), */ + _PAD_CFG_STRUCT(GPP_D8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D9 - GPIO */ + /* PAD_NC(GPP_D9, NONE), */ + _PAD_CFG_STRUCT(GPP_D9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D10 - GPIO */ + /* PAD_NC(GPP_D10, NONE), */ + _PAD_CFG_STRUCT(GPP_D10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D11 - GPIO */ + /* PAD_NC(GPP_D11, NONE), */ + _PAD_CFG_STRUCT(GPP_D11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D12 - GPIO */ + /* PAD_NC(GPP_D12, NONE), */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D13 - GPIO */ + /* PAD_NC(GPP_D13, NONE), */ + _PAD_CFG_STRUCT(GPP_D13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D14 - GPIO */ + /* PAD_NC(GPP_D14, NONE), */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D15 - GPIO */ + /* PAD_NC(GPP_D15, NONE), */ + _PAD_CFG_STRUCT(GPP_D15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D16 - GPIO */ + /* PAD_NC(GPP_D16, NONE), */ + _PAD_CFG_STRUCT(GPP_D16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D17 - GPIO */ + /* PAD_NC(GPP_D17, NONE), */ + _PAD_CFG_STRUCT(GPP_D17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D18 - GPIO */ + /* PAD_CFG_GPO(GPP_D18, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D19 - GPIO */ + /* PAD_CFG_GPO(GPP_D19, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_D20 - GPIO */ + /* PAD_NC(GPP_D20, NONE), */ + _PAD_CFG_STRUCT(GPP_D20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D21 - GPIO */ + /* PAD_CFG_GPO(GPP_D21, 0, DEEP), */ + _PAD_CFG_STRUCT(GPP_D21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_D22 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_D22, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_D23 - GPIO */ + /* PAD_NC(GPP_D23, NONE), */ + _PAD_CFG_STRUCT(GPP_D23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E0 - SATAXPCIE0 */ + /* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_E1 - GPIO */ + /* PAD_NC(GPP_E1, NONE), */ + _PAD_CFG_STRUCT(GPP_E1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E2 - GPIO */ + /* PAD_NC(GPP_E2, NONE), */ + _PAD_CFG_STRUCT(GPP_E2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E3 - GPIO */ + /* PAD_NC(GPP_E3, NONE), */ + _PAD_CFG_STRUCT(GPP_E3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E4 - GPIO */ + /* PAD_NC(GPP_E4, NONE), */ + _PAD_CFG_STRUCT(GPP_E4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E5 - GPIO */ + /* PAD_NC(GPP_E5, NONE), */ + _PAD_CFG_STRUCT(GPP_E5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E6 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_E6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1), + PAD_PULL(20K_PU)), + + /* GPP_E7 - GPIO */ + /* PAD_NC(GPP_E7, NONE), */ + _PAD_CFG_STRUCT(GPP_E7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E8 - SATA_LED# */ + /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_E9 - USB_OC0# */ + /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E10 - USB_OC1# */ + /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E11 - USB_OC2# */ + /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_E12 - USB_OC3# */ + /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F0 - GPIO */ + /* PAD_NC(GPP_F0, NONE), */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F1 - GPIO */ + /* PAD_NC(GPP_F1, NONE), */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F2 - GPIO */ + /* PAD_NC(GPP_F2, NONE), */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F3 - GPIO */ + /* PAD_NC(GPP_F3, NONE), */ + _PAD_CFG_STRUCT(GPP_F3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F4 - GPIO */ + /* PAD_NC(GPP_F4, NONE), */ + _PAD_CFG_STRUCT(GPP_F4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F5 - GPIO */ + /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F6 - GPIO */ + /* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F7 - GPIO */ + /* PAD_CFG_GPO(GPP_F7, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F8 - GPIO */ + /* PAD_CFG_GPO(GPP_F8, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_F9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F10 - SATA_SCLOCK */ + /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F11 - SATA_SLOAD */ + /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F12 - SATA_SDATAOUT1 */ + /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F13 - SATA_SDATAOUT2 */ + /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F14 - GPIO */ + /* PAD_NC(GPP_F14, NONE), */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F15 - USB_OC4# */ + /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F16 - USB_OC5# */ + /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_F17 - GPIO */ + /* PAD_NC(GPP_F17, NONE), */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F18 - GPIO */ + /* PAD_NC(GPP_F18, NONE), */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F19 - GPIO */ + /* PAD_NC(GPP_F19, NONE), */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F20 - GPIO */ + /* PAD_NC(GPP_F20, NONE), */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F21 - GPIO */ + /* PAD_NC(GPP_F21, NONE), */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F22 - GPIO */ + /* PAD_NC(GPP_F22, NONE), */ + _PAD_CFG_STRUCT(GPP_F22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_F23 - GPIO */ + /* PAD_CFG_GPO(GPP_F23, 0, RSMRST), */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_G0 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G2 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G3 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G4 - GPIO */ + /* PAD_NC(GPP_G4, NONE), */ + _PAD_CFG_STRUCT(GPP_G4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G5 - GPIO */ + /* PAD_NC(GPP_G5, NONE), */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G6 - GPIO */ + /* PAD_NC(GPP_G6, NONE), */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G7 - GPIO */ + /* PAD_NC(GPP_G7, NONE), */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G8 - GPIO */ + /* PAD_NC(GPP_G8, NONE), */ + _PAD_CFG_STRUCT(GPP_G8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G9 - GPIO */ + /* PAD_NC(GPP_G9, NONE), */ + _PAD_CFG_STRUCT(GPP_G9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G10 - GPIO */ + /* PAD_NC(GPP_G10, NONE), */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G11 - GPIO */ + /* PAD_NC(GPP_G11, NONE), */ + _PAD_CFG_STRUCT(GPP_G11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G12 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G13 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G14 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_G15 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G16 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_G16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + + /* GPP_G17 - GPIO */ + /* PAD_NC(GPP_G17, NONE), */ + _PAD_CFG_STRUCT(GPP_G17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G18 - NMI# */ + /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G18, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G19 - SMI# */ + /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G19, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G20 - GPIO */ + /* PAD_NC(GPP_G20, NONE), */ + _PAD_CFG_STRUCT(GPP_G20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G21 - GPIO */ + /* PAD_NC(GPP_G21, NONE), */ + _PAD_CFG_STRUCT(GPP_G21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G22 - GPIO */ + /* PAD_NC(GPP_G22, NONE), */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G23 - GPIO */ + /* PAD_NC(GPP_G23, NONE), */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H0 - GPIO */ + /* PAD_CFG_GPO(GPP_H0, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + + /* GPP_H2 - GPIO */ + /* PAD_CFG_GPO(GPP_H2, 1, DEEP), */ + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H3 - SRCCLKREQ9# */ + /* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + + /* GPP_H4 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), + + /* GPP_H5 - GPIO */ + /* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H6 - GPIO */ + /* PAD_CFG_GPO(GPP_H6, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H7 - GPIO */ + /* PAD_CFG_GPO(GPP_H7, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H8 - GPIO */ + /* PAD_CFG_GPO(GPP_H8, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H9 - GPIO */ + /* PAD_CFG_GPO(GPP_H9, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H10 - SML2CLK */ + /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H11 - SML2DATA */ + /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H12 - GPIO */ + /* PAD_NC(GPP_H12, NONE), */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H13 - SML3CLK */ + /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H14 - SML3DATA */ + /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H15 - GPIO */ + /* PAD_NC(GPP_H15, NONE), */ + _PAD_CFG_STRUCT(GPP_H15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H16 - SML4CLK */ + /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H17 - SML4DATA */ + /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H17, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H18 - GPIO */ + /* PAD_NC(GPP_H18, NONE), */ + _PAD_CFG_STRUCT(GPP_H18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_H19 - GPIO */ + /* PAD_CFG_GPO(GPP_H19, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H20 - GPIO */ + /* PAD_CFG_GPO(GPP_H20, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H21 - GPIO */ + /* PAD_CFG_GPO(GPP_H21, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H22 - GPIO */ + /* PAD_CFG_GPO(GPP_H22, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPP_H23 - GPIO */ + /* PAD_CFG_GPO(GPP_H23, 1, PLTRST), */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + + /* GPD0 - GPIO */ + /* PAD_NC(GPD0, NONE), */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD1 - GPIO */ + /* PAD_NC(GPD1, NONE), */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD2 - LAN_WAKE# */ + /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD2, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPD3 - PWRBTN# */ + /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD3, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPD4 - SLP_S3# */ + /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD4, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD5 - SLP_S4# */ + /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD5, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD6 - SLP_A# */ + /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD6, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD7 - GPIO */ + /* PAD_NC(GPD7, NONE), */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* GPD8 - SUSCLK */ + /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD9 - GPIO */ + /* PAD_NC(GPD9, NONE), */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD10 - GPIO */ + /* PAD_NC(GPD10, NONE), */ + _PAD_CFG_STRUCT(GPD10, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPD11 - GPIO */ + /* PAD_NC(GPD11, NONE), */ + _PAD_CFG_STRUCT(GPD11, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I0 - DDPB_HPD0 */ + /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I1 - DDPC_HPD1 */ + /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I2 - DDPD_HPD2 */ + /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I3 - DDPE_HPD3 */ + /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I4 - GPIO */ + /* PAD_NC(GPP_I4, NONE), */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I5 - DDPB_CTRLCLK */ + /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I6 - DDPB_CTRLDATA */ + /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I7 - DDPC_CTRLCLK */ + /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I8 - DDPC_CTRLDATA */ + /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I9 - DDPD_CTRLCLK */ + /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_I10 - DDPD_CTRLDATA */ + /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), };
/*** XXX TODO XXX */ /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* LPC */ + /* LPC */
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), };
#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 0c47a9d..400bf7a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -6,251 +6,1306 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* Pad configuration was generated automatically using intelp2m utility. */ static const struct pad_config gpio_table[] = { /* GPIO Group GPP_A */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x00000010), /* RCIN# */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x00000010), /* PIRQA# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x00000010), /* PME# */ - _PAD_CFG_STRUCT(GPP_A12, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000010), /* SUSWARN#/SUSPWRDNACK */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000010), /* SUS_STAT# */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000010), /* SUS_ACK# */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000010), /* CLKOUT_48 */ - _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffffff), /* ISH_GP1 */ - _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_A0 - RCIN# */ + /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A7 - PIRQA# */ + /* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A11 - PME# */ + /* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A12 - GPIO */ + /* PAD_NC(GPP_A12, NONE), */ + _PAD_CFG_STRUCT(GPP_A12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A14 - SUS_STAT# */ + /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A15 - SUS_ACK# */ + /* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A16 - CLKOUT_48 */ + /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A17 - GPIO */ + /* PAD_NC(GPP_A17, NONE), */ + _PAD_CFG_STRUCT(GPP_A17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A18 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_A18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A19 - ISH_GP1 (RESERVED) */ + + /* GPP_A20 - GPIO */ + /* PAD_NC(GPP_A20, NONE), */ + _PAD_CFG_STRUCT(GPP_A20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A21 - GPIO */ + /* PAD_NC(GPP_A21, NONE), */ + _PAD_CFG_STRUCT(GPP_A21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A22 - GPIO */ + /* PAD_NC(GPP_A22, NONE), */ + _PAD_CFG_STRUCT(GPP_A22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A23 - GPIO */ + /* PAD_NC(GPP_A23, NONE), */ + _PAD_CFG_STRUCT(GPP_A23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_B */ - _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000010), /* SLP_S0# */ - _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000010), /* PLTRST# */ - _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000010), /* SPKR */ - _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000010), /* PCHHOT# */ + + /* GPP_B0 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B1 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B2 - GPIO */ + /* PAD_NC(GPP_B2, NONE), */ + _PAD_CFG_STRUCT(GPP_B2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B3 - GPIO */ + /* PAD_NC(GPP_B3, NONE), */ + _PAD_CFG_STRUCT(GPP_B3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B4 - GPIO */ + /* PAD_NC(GPP_B4, NONE), */ + _PAD_CFG_STRUCT(GPP_B4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B5 - GPIO */ + /* PAD_NC(GPP_B5, NONE), */ + _PAD_CFG_STRUCT(GPP_B5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B6 - GPIO */ + /* PAD_NC(GPP_B6, NONE), */ + _PAD_CFG_STRUCT(GPP_B6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B7 - GPIO */ + /* PAD_NC(GPP_B7, NONE), */ + _PAD_CFG_STRUCT(GPP_B7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B8 - GPIO */ + /* PAD_NC(GPP_B8, NONE), */ + _PAD_CFG_STRUCT(GPP_B8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B9 - GPIO */ + /* PAD_NC(GPP_B9, NONE), */ + _PAD_CFG_STRUCT(GPP_B9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B10 - GPIO */ + /* PAD_NC(GPP_B10, NONE), */ + _PAD_CFG_STRUCT(GPP_B10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B11 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B12 - SLP_S0# */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B13 - PLTRST# */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B14 - SPKR */ + /* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_B14, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B15 - GPIO */ + /* PAD_NC(GPP_B15, NONE), */ + _PAD_CFG_STRUCT(GPP_B15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B16 - GPIO */ + /* PAD_NC(GPP_B16, NONE), */ + _PAD_CFG_STRUCT(GPP_B16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B17 - GPIO */ + /* PAD_NC(GPP_B17, NONE), */ + _PAD_CFG_STRUCT(GPP_B17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B18 - GPIO */ + /* PAD_NC(GPP_B18, NONE), */ + _PAD_CFG_STRUCT(GPP_B18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B19 - GPIO */ + /* PAD_NC(GPP_B19, NONE), */ + _PAD_CFG_STRUCT(GPP_B19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B20 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_B20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B21 - GPIO */ + /* PAD_NC(GPP_B21, NONE), */ + _PAD_CFG_STRUCT(GPP_B21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B22 - GPIO */ + /* PAD_NC(GPP_B22, NONE), */ + _PAD_CFG_STRUCT(GPP_B22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_B23 - PCHHOT# */ + /* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_C */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x00000010), /* SMBCLK */ - //_PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x00000010), /* SMBDATA */ - _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x00000010), /* SML0CLK */ - //_PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x00000010), /* SML0DATA */ - _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000010), /* GPIO */ - /* reserved */ - //_PAD_CFG_STRUCT(GPP_C6, 0x44000700, 0x00000010), /* SML1CLK */ - //_PAD_CFG_STRUCT(GPP_C7, 0x44000700, 0x00000010), /* SML1DATA */ - _PAD_CFG_STRUCT(GPP_C8, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x42040100, 0x00003010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000010), /* GPIO */ + + /* GPP_C0 - SMBCLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C0, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C1 - SMBDATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C1, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C2 - GPIO */ + /* PAD_NC(GPP_C2, NONE), */ + _PAD_CFG_STRUCT(GPP_C2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C3 - SML0CLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C3, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C4 - SML0DATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C4, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C5 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C6 - SML1CLK (RESERVED) */ + /* PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C6, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C7 - SML1DATA (RESERVED) */ + /* PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), */ + //_PAD_CFG_STRUCT(GPP_C7, + // PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C8 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C10 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C11 - GPIO */ + /* PAD_NC(GPP_C11, NONE), */ + _PAD_CFG_STRUCT(GPP_C11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C12 - GPIO */ + /* PAD_NC(GPP_C12, NONE), */ + _PAD_CFG_STRUCT(GPP_C12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C13 - GPIO */ + /* PAD_NC(GPP_C13, NONE), */ + _PAD_CFG_STRUCT(GPP_C13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C14 - GPIO */ + /* PAD_NC(GPP_C14, NONE), */ + _PAD_CFG_STRUCT(GPP_C14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C15 - GPIO */ + /* PAD_NC(GPP_C15, NONE), */ + _PAD_CFG_STRUCT(GPP_C15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C16 - GPIO */ + /* PAD_NC(GPP_C16, NONE), */ + _PAD_CFG_STRUCT(GPP_C16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C17 - GPIO */ + /* PAD_NC(GPP_C17, NONE), */ + _PAD_CFG_STRUCT(GPP_C17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C18 - GPIO */ + /* PAD_NC(GPP_C18, NONE), */ + _PAD_CFG_STRUCT(GPP_C18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C19 - GPIO */ + /* PAD_NC(GPP_C19, NONE), */ + _PAD_CFG_STRUCT(GPP_C19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C20 - GPIO */ + /* PAD_NC(GPP_C20, NONE), */ + _PAD_CFG_STRUCT(GPP_C20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C21 - GPIO */ + /* PAD_NC(GPP_C21, NONE), */ + _PAD_CFG_STRUCT(GPP_C21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C22 - GPIO */ + /* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_C22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU) | PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_C23 - GPIO */ + /* PAD_NC(GPP_C23, NONE), */ + _PAD_CFG_STRUCT(GPP_C23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_D */ - _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x42020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0xc4000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_D0 - GPIO */ + /* PAD_NC(GPP_D0, NONE), */ + _PAD_CFG_STRUCT(GPP_D0, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D1 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_D1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D2 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_D2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU)), + + /* GPP_D3 - GPIO */ + /* PAD_NC(GPP_D3, NONE), */ + _PAD_CFG_STRUCT(GPP_D3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D4 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D5 - GPIO */ + /* PAD_NC(GPP_D5, NONE), */ + _PAD_CFG_STRUCT(GPP_D5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D6 - GPIO */ + /* PAD_NC(GPP_D6, NONE), */ + _PAD_CFG_STRUCT(GPP_D6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D7 - GPIO */ + /* PAD_NC(GPP_D7, NONE), */ + _PAD_CFG_STRUCT(GPP_D7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D8 - GPIO */ + /* PAD_NC(GPP_D8, NONE), */ + _PAD_CFG_STRUCT(GPP_D8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D9 - GPIO */ + /* PAD_NC(GPP_D9, NONE), */ + _PAD_CFG_STRUCT(GPP_D9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D10 - GPIO */ + /* PAD_NC(GPP_D10, NONE), */ + _PAD_CFG_STRUCT(GPP_D10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D11 - GPIO */ + /* PAD_NC(GPP_D11, NONE), */ + _PAD_CFG_STRUCT(GPP_D11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D12 - GPIO */ + /* PAD_NC(GPP_D12, NONE), */ + _PAD_CFG_STRUCT(GPP_D12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D13 - GPIO */ + /* PAD_NC(GPP_D13, NONE), */ + _PAD_CFG_STRUCT(GPP_D13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D14 - GPIO */ + /* PAD_NC(GPP_D14, NONE), */ + _PAD_CFG_STRUCT(GPP_D14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D15 - GPIO */ + /* PAD_NC(GPP_D15, NONE), */ + _PAD_CFG_STRUCT(GPP_D15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D16 - GPIO */ + /* PAD_NC(GPP_D16, NONE), */ + _PAD_CFG_STRUCT(GPP_D16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D17 - GPIO */ + /* PAD_NC(GPP_D17, NONE), */ + _PAD_CFG_STRUCT(GPP_D17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D18 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D18, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D19 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_D19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D20 - GPIO */ + /* PAD_NC(GPP_D20, NONE), */ + _PAD_CFG_STRUCT(GPP_D20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D21 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_D21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D22 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, DRIVER) */ + _PAD_CFG_STRUCT(GPP_D22, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_D23 - GPIO */ + /* PAD_NC(GPP_D23, NONE), */ + _PAD_CFG_STRUCT(GPP_D23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_E */ - _PAD_CFG_STRUCT(GPP_E0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x82020100, 0x00003000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000010), /* SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E9, 0x44000700, 0x00000010), /* USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E10, 0x44000700, 0x00000010), /* USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E11, 0x44000700, 0x00000010), /* USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E12, 0x44000700, 0x00000010), /* USB_OC3# */ + + /* GPP_E0 - GPIO */ + /* PAD_NC(GPP_E0, NONE), */ + _PAD_CFG_STRUCT(GPP_E0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E1 - GPIO */ + /* PAD_NC(GPP_E1, NONE), */ + _PAD_CFG_STRUCT(GPP_E1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E2 - GPIO */ + /* PAD_NC(GPP_E2, NONE), */ + _PAD_CFG_STRUCT(GPP_E2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E3 - GPIO */ + /* PAD_NC(GPP_E3, NONE), */ + _PAD_CFG_STRUCT(GPP_E3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E4 - GPIO */ + /* PAD_NC(GPP_E4, NONE), */ + _PAD_CFG_STRUCT(GPP_E4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E5 - GPIO */ + /* PAD_NC(GPP_E5, NONE), */ + _PAD_CFG_STRUCT(GPP_E5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E6 - GPIO */ + /* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */ + _PAD_CFG_STRUCT(GPP_E6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE), + PAD_PULL(20K_PU)), + + /* GPP_E7 - GPIO */ + /* PAD_NC(GPP_E7, NONE), */ + _PAD_CFG_STRUCT(GPP_E7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E8 - SATA_LED# */ + /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E9 - USB_OC0# */ + /* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E10 - USB_OC1# */ + /* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E11 - USB_OC2# */ + /* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_E12 - USB_OC3# */ + /* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_F */ - _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x80100100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000010), /* SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000010), /* SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000010), /* SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000010), /* SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x00000010), /* USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x00000010), /* USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_F23, 0xc4000200, 0x00000010), /* GPIO */ + + /* GPP_F0 - GPIO */ + /* PAD_NC(GPP_F0, NONE), */ + _PAD_CFG_STRUCT(GPP_F0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F1 - GPIO */ + /* PAD_NC(GPP_F1, NONE), */ + _PAD_CFG_STRUCT(GPP_F1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F2 - GPIO */ + /* PAD_NC(GPP_F2, NONE), */ + _PAD_CFG_STRUCT(GPP_F2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F3 - GPIO */ + /* PAD_NC(GPP_F3, NONE), */ + _PAD_CFG_STRUCT(GPP_F3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F4 - GPIO */ + /* PAD_NC(GPP_F4, NONE), */ + _PAD_CFG_STRUCT(GPP_F4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F5 - GPIO */ + /* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */ + _PAD_CFG_STRUCT(GPP_F5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F6 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F7 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F8 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F9 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_F9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F10 - SATA_SCLOCK */ + /* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F11 - SATA_SLOAD */ + /* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F12 - SATA_SDATAOUT1 */ + /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F12, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F13 - SATA_SDATAOUT2 */ + /* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F14 - GPIO */ + /* PAD_NC(GPP_F14, NONE), */ + _PAD_CFG_STRUCT(GPP_F14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F15 - USB_OC4# */ + /* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F15, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F16 - USB_OC5# */ + /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F17 - GPIO */ + /* PAD_NC(GPP_F17, NONE), */ + _PAD_CFG_STRUCT(GPP_F17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F18 - GPIO */ + /* PAD_NC(GPP_F18, NONE), */ + _PAD_CFG_STRUCT(GPP_F18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F19 - GPIO */ + /* PAD_NC(GPP_F19, NONE), */ + _PAD_CFG_STRUCT(GPP_F19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F20 - GPIO */ + /* PAD_NC(GPP_F20, NONE), */ + _PAD_CFG_STRUCT(GPP_F20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F21 - GPIO */ + /* PAD_NC(GPP_F21, NONE), */ + _PAD_CFG_STRUCT(GPP_F21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F22 - GPIO */ + /* PAD_NC(GPP_F22, NONE), */ + _PAD_CFG_STRUCT(GPP_F22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_F23 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), */ + _PAD_CFG_STRUCT(GPP_F23, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_G */ - _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000010), /* NMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000010), /* SMI# */ - _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), /* GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000010), /* GPIO */ + + /* GPP_G0 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G1, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G2 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G3 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G4 - GPIO */ + /* PAD_NC(GPP_G4, NONE), */ + _PAD_CFG_STRUCT(GPP_G4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G5 - GPIO */ + /* PAD_NC(GPP_G5, NONE), */ + _PAD_CFG_STRUCT(GPP_G5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G6 - GPIO */ + /* PAD_NC(GPP_G6, NONE), */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G7 - GPIO */ + /* PAD_NC(GPP_G7, NONE), */ + _PAD_CFG_STRUCT(GPP_G7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G8 - GPIO */ + /* PAD_NC(GPP_G8, NONE), */ + _PAD_CFG_STRUCT(GPP_G8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G9 - GPIO */ + /* PAD_NC(GPP_G9, NONE), */ + _PAD_CFG_STRUCT(GPP_G9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G10 - GPIO */ + /* PAD_NC(GPP_G10, NONE), */ + _PAD_CFG_STRUCT(GPP_G10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G11 - GPIO */ + /* PAD_NC(GPP_G11, NONE), */ + _PAD_CFG_STRUCT(GPP_G11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G12 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G13 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G13, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G14 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G15 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G15, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G16 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_G16, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G17 - GPIO */ + /* PAD_NC(GPP_G17, NONE), */ + _PAD_CFG_STRUCT(GPP_G17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G18 - NMI# */ + /* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G18, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G19 - SMI# */ + /* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_G19, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_G20 - GPIO */ + /* PAD_NC(GPP_G20, NONE), */ + _PAD_CFG_STRUCT(GPP_G20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G21 - GPIO */ + /* PAD_NC(GPP_G21, NONE), */ + _PAD_CFG_STRUCT(GPP_G21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G22 - GPIO */ + /* PAD_NC(GPP_G22, NONE), */ + _PAD_CFG_STRUCT(GPP_G22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_G23 - GPIO */ + /* PAD_NC(GPP_G23, NONE), */ + _PAD_CFG_STRUCT(GPP_G23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_H */ - _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x44000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x84000101, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H10, 0x44000700, 0x00000010), /* SML2CLK */ - _PAD_CFG_STRUCT(GPP_H11, 0x44000700, 0x00000010), /* SML2DATA */ - _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H13, 0x44000700, 0x00000010), /* SML3CLK */ - _PAD_CFG_STRUCT(GPP_H14, 0x44000700, 0x00000010), /* SML3DATA */ - _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H16, 0x44000700, 0x00000010), /* SML4CLK */ - _PAD_CFG_STRUCT(GPP_H17, 0x44000700, 0x00000010), /* SML4DATA */ - _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000010), /* GPIO */ + + /* GPP_H0 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H1 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_H1, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H2 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H3 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), */ + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H4 - GPIO */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, DRIVER), */ + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H5 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H5, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H6 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H6, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H7 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H8 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H8, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H9 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H10 - SML2CLK */ + /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H11 - SML2DATA */ + /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H11, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H12 - GPIO */ + /* PAD_NC(GPP_H12, NONE), */ + _PAD_CFG_STRUCT(GPP_H12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H13 - SML3CLK */ + /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H13, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H14 - SML3DATA */ + /* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H14, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H15 - GPIO */ + /* PAD_NC(GPP_H15, NONE), */ + _PAD_CFG_STRUCT(GPP_H15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H16 - SML4CLK */ + /* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H16, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H17 - SML4DATA */ + /* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H17, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H18 - GPIO */ + /* PAD_NC(GPP_H18, NONE), */ + _PAD_CFG_STRUCT(GPP_H18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H19 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H19, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H20 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H20, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H21 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H21, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H22 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H22, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_H23 - GPIO */ + /* PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), */ + _PAD_CFG_STRUCT(GPP_H23, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPP_I */ - _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000010), /* DDPB_HPD0 */ - _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000010), /* DDPC_HPD1 */ - _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000010), /* DDPD_HPD2 */ - _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000010), /* DDPE_HPD3 */ - _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000010), /* DDPB_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000010), /* DDPB_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000010), /* DDPC_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000010), /* DDPC_CTRLDATA */ - _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000010), /* DDPD_CTRLCLK */ - _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000010), /* DDPD_CTRLDATA */ + + /* GPP_I0 - DDPB_HPD0 */ + /* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I1 - DDPC_HPD1 */ + /* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I2 - DDPD_HPD2 */ + /* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I3 - DDPE_HPD3 */ + /* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_I3, + PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I4 - GPIO */ + /* PAD_NC(GPP_I4, NONE), */ + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I5 - DDPB_CTRLCLK */ + /* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I6 - DDPB_CTRLDATA */ + /* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I7 - DDPC_CTRLCLK */ + /* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I7, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I8 - DDPC_CTRLDATA */ + /* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I9 - DDPD_CTRLCLK */ + /* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_I10 - DDPD_CTRLDATA */ + /* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_I10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* GPIO Group GPD */ - _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD2, 0x04000700, 0x00000010), /* LAN_WAKE# */ - _PAD_CFG_STRUCT(GPD3, 0x04000700, 0x00000010), /* PWRBTN# */ - _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000010), /* SLP_S3# */ - _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000010), /* SLP_S4# */ - _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000010), /* SLP_A# */ - _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000010), /* SUSCLK */ - _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000010), /* GPIO */ - _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000010), /* GPIO */ + + /* GPD0 - GPIO */ + /* PAD_NC(GPD0, NONE), */ + _PAD_CFG_STRUCT(GPD0, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD1 - GPIO */ + /* PAD_NC(GPD1, NONE), */ + _PAD_CFG_STRUCT(GPD1, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD2 - LAN_WAKE# */ + /* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD2, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD3 - PWRBTN# */ + /* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD3, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD4 - SLP_S3# */ + /* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD4, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD5 - SLP_S4# */ + /* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD5, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD6 - SLP_A# */ + /* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD6, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD7 - GPIO */ + /* PAD_NC(GPD7, NONE), */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD8 - SUSCLK */ + /* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */ + _PAD_CFG_STRUCT(GPD8, + PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD9 - GPIO */ + /* PAD_NC(GPD9, NONE), */ + _PAD_CFG_STRUCT(GPD9, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD10 - GPIO */ + /* PAD_NC(GPD10, NONE), */ + _PAD_CFG_STRUCT(GPD10, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPD11 - GPIO */ + /* PAD_NC(GPD11, NONE), */ + _PAD_CFG_STRUCT(GPD11, + PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), };
/* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* GPIO Group GPP_A */ /* LPC */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x00000010), /* LAD0 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000010), /* LAD1 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x00000010), /* LAD2 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000010), /* LAD3 */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000010), /* LFRAME# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000010), /* CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000010), /* CLKOUT_LPC0 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000010), /* CLKOUT_LPC1 */ + + /* GPP_A1 - LAD0 */ + /* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A2 - LAD1 */ + /* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A3 - LAD2 */ + /* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A4 - LAD3 */ + /* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A4, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A5 - LFRAME# */ + /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A5, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A8 - CLKRUN# */ + /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)),
/* Serial interrupt */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000010), /* SERIRQ */ + + /* GPP_A6 - SERIRQ */ + /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A6, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_CFG_OWN_GPIO(DRIVER)), };
#endif /* _GPIO_X11SSM_F_H */
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