Change in coreboot[master]: soc/intel/alderlake: Update variable SD3C to only track enabled devices

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51965 )

Change subject: soc/intel/alderlake: Update variable SD3C to only track enabled devices
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soc/intel/alderlake: Update variable SD3C to only track enabled devices

Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.

BUG=None
TEST=Built Alderlake image successfully.

Signed-off-by: John Zhao 
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/acpi/tcss_pcierp.asl
1 file changed, 7 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 07d024a..589a3e9 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -76,10 +76,14 @@

Method (_DSW, 3)
 {
-	C2PM (Arg0, Arg1, Arg2, DCPM)
    /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
-	_SB.PCI0.TDM0.SD3C = Arg1
-	_SB.PCI0.TDM1.SD3C = Arg1
+	If ((TUID == 0) || (TUID == 1)) {
+		_SB.PCI0.TDM0.SD3C = Arg1
+	} Else {
+		_SB.PCI0.TDM1.SD3C = Arg1
+	}
+
+	C2PM (Arg0, Arg1, Arg2, DCPM)
 }

Method (_PRW, 0)