Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36888 )
Change subject: mb/compulab/intense_pc: Clean PCH and super-i/o config up ......................................................................
mb/compulab/intense_pc: Clean PCH and super-i/o config up
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's a 16-bit register and shouldn't be bluntly zeroed.
Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/compulab/intense_pc/early_init.c 1 file changed, 4 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36888/1
diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index 73acc46..cb5f445 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -23,27 +23,6 @@
#define SIO_PORT 0x164e
-void mainboard_pch_lpc_setup(void) -{ - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable SuperIO */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - -#if CONFIG(DRIVERS_UART_8250IO) - /* Enable COM1 */ - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -#endif -} - -void mainboard_late_rcba_config(void) -{ - RCBA32(0x3414) = 0x00000000; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, @@ -66,6 +45,10 @@ const u16 port = SIO_PORT; const u16 runtime_port = 0x180;
+ /* Enable COM1 if requested */ + if (CONFIG(DRIVERS_UART_8250IO)) + sio1007_enable_uart_at(port); + /* Turn on configuration mode. */ outb(0x55, port);
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36888 )
Change subject: mb/compulab/intense_pc: Clean PCH and super-i/o config up ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36888/1/src/mainboard/compulab/inte... File src/mainboard/compulab/intense_pc/early_init.c:
https://review.coreboot.org/c/coreboot/+/36888/1/src/mainboard/compulab/inte... PS1, Line 36: if (sio1007_enable_uart_at(SIO_PORT)) { : pci_write_config16(dev, LPC_EN, : lpc_config | COMA_LPC_EN); I thought it was here to avoid LPC decoding COMA if something went wrong with the superio. It's probably overscrupulous.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36888 )
Change subject: mb/compulab/intense_pc: Clean PCH and super-i/o config up ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36888/1/src/mainboard/compulab/inte... File src/mainboard/compulab/intense_pc/early_init.c:
https://review.coreboot.org/c/coreboot/+/36888/1/src/mainboard/compulab/inte... PS1, Line 36: if (sio1007_enable_uart_at(SIO_PORT)) { : pci_write_config16(dev, LPC_EN, : lpc_config | COMA_LPC_EN);
I thought it was here to avoid LPC decoding COMA if something went wrong with the superio. […]
Done
Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36888
to look at the new patch set (#2).
Change subject: mb/compulab/intense_pc: Clean PCH and super-i/o config up ......................................................................
mb/compulab/intense_pc: Clean PCH and super-i/o config up
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed.
Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/compulab/intense_pc/early_init.c 1 file changed, 4 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36888/2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36888 )
Change subject: mb/compulab/intense_pc: Clean PCH and super-i/o config up ......................................................................
mb/compulab/intense_pc: Clean PCH and super-i/o config up
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed.
Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/compulab/intense_pc/early_init.c 1 file changed, 4 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index 73acc46..cb5f445 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -23,27 +23,6 @@
#define SIO_PORT 0x164e
-void mainboard_pch_lpc_setup(void) -{ - pci_devfn_t dev = PCH_LPC_DEV; - - /* Enable SuperIO */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); - -#if CONFIG(DRIVERS_UART_8250IO) - /* Enable COM1 */ - if (sio1007_enable_uart_at(SIO_PORT)) { - pci_write_config16(dev, LPC_EN, - lpc_config | COMA_LPC_EN); - } -#endif -} - -void mainboard_late_rcba_config(void) -{ - RCBA32(0x3414) = 0x00000000; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, { 1, 1, 0 }, @@ -66,6 +45,10 @@ const u16 port = SIO_PORT; const u16 runtime_port = 0x180;
+ /* Enable COM1 if requested */ + if (CONFIG(DRIVERS_UART_8250IO)) + sio1007_enable_uart_at(port); + /* Turn on configuration mode. */ outb(0x55, port);
-
Arthur Heymans (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)