Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46960 )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl 2 files changed, 77 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46960/1
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc2..134a7cf 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -27,6 +27,25 @@ , 5, HPTE, 1, // Address Enable } + + /* + * Check PCH type + * Return 1 if PCH is WildcatPoint + * Return 0 if PCH is LynxPoint + */ +#if CONFIG(INTEL_LYNXPOINT_LP) + Method (ISWP) + { + Local0 = _SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { + Return (1) + } Else { + Return (0) + } + } +#else + Name (ISWP, 0) +#endif }
// High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 2b3d433..203ee3b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -17,6 +17,14 @@ Offset (0x10), , 16, XMEM, 16, // MEM_BASE + Offset (0x40), + , 11, + SWAI, 1, + , 20, + Offset (0x44), + , 12, + SAIP, 2, + , 18, Offset (0x74), D0D3, 2, , 6, @@ -214,25 +222,39 @@ }
#if CONFIG(INTEL_LYNXPOINT_LP) - // Clear PCI 0xB0[14:13] - ^MB13 = 0 - ^MB14 = 0 + If (!\ISWP()) { + // Clear PCI 0xB0[14:13] + ^MB13 = 0 + ^MB14 = 0
- // Clear MMIO 0x816C[14,2] - CLK0 = 0 - CLK1 = 0 + // Clear MMIO 0x816C[14,2] + CLK0 = 0 + CLK1 = 0
- // Set MMIO 0x8154[31] - CLK2 = 1 + // Set MMIO 0x8154[31] + CLK2 = 1
- // Handle per-port reset if needed - LPS0 () + // Handle per-port reset if needed + LPS0 ()
- // Set MMIO 0x80e0[15] - AX15 = 1 + // Set MMIO 0x80e0[15] + AX15 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 + } #else // Set MMIO 0x8154[31] CLK2 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 #endif
Return () @@ -273,22 +295,36 @@ }
#if CONFIG(INTEL_LYNXPOINT_LP) - // Set PCI 0xB0[14:13] - ^MB13 = 1 - ^MB14 = 1 + If (!\ISWP()) { + // Set PCI 0xB0[14:13] + ^MB13 = 1 + ^MB14 = 1
- // Set MMIO 0x816C[14,2] - CLK0 = 1 - CLK1 = 1 + // Set MMIO 0x816C[14,2] + CLK0 = 1 + CLK1 = 1
- // Clear MMIO 0x8154[31] - CLK2 = 0 + // Clear MMIO 0x8154[31] + CLK2 = 0
- // Clear MMIO 0x80e0[15] - AX15 = 0 + // Clear MMIO 0x80e0[15] + AX15 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 + } #else // Clear MMIO 0x8154[31] CLK2 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 #endif
// Put device in D3
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46960
to look at the new patch set (#5).
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl 2 files changed, 77 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46960/5
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Abandoned
Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Restored
Attention is currently required from: Angel Pons.
Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7: Looks fine to me. I'm not sure why it sat unreviewed for 2 years.
If anyone sees an issue with this, please comment. Otherwise this comment can be closed and the patch can be merged.
Attention is currently required from: Angel Pons, Martin L Roth.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Looks fine to me. I'm not sure why it sat unreviewed for 2 years. […]
let me take a closer look, LP-lp has always had some XHCI issues on google/slippy for which I've just used the BDW code instead
Attention is currently required from: Angel Pons, Martin L Roth.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
let me take a closer look, LP-lp has always had some XHCI issues on google/slippy for which I've jus […]
tested on google/slippy/var/wolf, no regressions that I see. LGTM
Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT
Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds.
Also, add the `ISWP` object (Name or Method) to test for WildcatPoint.
Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960 Reviewed-by: Martin L Roth gaumless@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/xhci.asl 2 files changed, 69 insertions(+), 22 deletions(-)
Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 8c76002..7ac35d6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,6 +19,25 @@ , 5, HPTE, 1, // Address Enable } + + /* + * Check PCH type + * Return 1 if PCH is WildcatPoint + * Return 0 if PCH is LynxPoint + */ +#if CONFIG(INTEL_LYNXPOINT_LP) + Method (ISWP) + { + Local0 = _SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { + Return (1) + } Else { + Return (0) + } + } +#else + Name (ISWP, 0) +#endif }
// High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index eec92c3..c7b0c18 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -221,25 +221,39 @@ }
#if CONFIG(INTEL_LYNXPOINT_LP) - // Clear PCI 0xB0[14:13] - ^MB13 = 0 - ^MB14 = 0 + If (!\ISWP()) { + // Clear PCI 0xB0[14:13] + ^MB13 = 0 + ^MB14 = 0
- // Clear MMIO 0x816C[14,2] - CLK0 = 0 - CLK1 = 0 + // Clear MMIO 0x816C[14,2] + CLK0 = 0 + CLK1 = 0
- // Set MMIO 0x8154[31] - CLK2 = 1 + // Set MMIO 0x8154[31] + CLK2 = 1
- // Handle per-port reset if needed - LPS0 () + // Handle per-port reset if needed + LPS0 ()
- // Set MMIO 0x80e0[15] - AX15 = 1 + // Set MMIO 0x80e0[15] + AX15 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 + } #else // Set MMIO 0x8154[31] CLK2 = 1 + + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 #endif
// Clear PCI CFG offset 0x40[11] @@ -286,22 +300,36 @@ }
#if CONFIG(INTEL_LYNXPOINT_LP) - // Set PCI 0xB0[14:13] - ^MB13 = 1 - ^MB14 = 1 + If (!\ISWP()) { + // Set PCI 0xB0[14:13] + ^MB13 = 1 + ^MB14 = 1
- // Set MMIO 0x816C[14,2] - CLK0 = 1 - CLK1 = 1 + // Set MMIO 0x816C[14,2] + CLK0 = 1 + CLK1 = 1
- // Clear MMIO 0x8154[31] - CLK2 = 0 + // Clear MMIO 0x8154[31] + CLK2 = 0
- // Clear MMIO 0x80e0[15] - AX15 = 0 + // Clear MMIO 0x80e0[15] + AX15 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 + } #else // Clear MMIO 0x8154[31] CLK2 = 0 + + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 #endif
// Set PCI CFG offset 0x40[11]
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46960?usp=email )
Change subject: sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPT ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 4 / 10
FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/178981 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/178980 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/178979 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/178978 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/178977 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/178976 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/178975 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/178974 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/178973 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/178972
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Martin L Roth (Code Review)
-
Matt DeVillier (Code Review)
-
Stefan Reinauer (Code Review)