Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
Tis is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration.
Tested on Prodrive Hermes.
Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46562/1
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ae9f650..f97defb 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -76,6 +76,7 @@
static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_SMBUS, + PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER,
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46562/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46562/1//COMMIT_MSG@9 PS1, Line 9: eve nit: wrap at 72 characters
(sorry if I'm too obstinate with this, but this line wraps for me on Gerrit)
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46562
to look at the new patch set (#2).
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
Tis is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration.
Tested on Prodrive Hermes.
Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46562/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46562/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46562/1//COMMIT_MSG@9 PS1, Line 9: eve
nit: wrap at 72 characters […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Sorry, I only just saw this
https://review.coreboot.org/c/coreboot/+/46562/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46562/2//COMMIT_MSG@9 PS2, Line 9: Tis T*h*is
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46562
to look at the new patch set (#3).
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
This is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration.
Tested on Prodrive Hermes.
Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46562/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46562/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46562/2//COMMIT_MSG@9 PS2, Line 9: Tis
T*h*is
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46562 )
Change subject: soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID ......................................................................
soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
This is required to make sure the defined SMBUS_BASE address is valid even after PCI enumeration.
Tested on Prodrive Hermes.
Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 8ba9d7a..59870fb 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -77,6 +77,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_SMBUS, PCI_DEVICE_ID_INTEL_CNL_SMBUS, + PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER,
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Angel Pons (Code Review) -
Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)