Change in coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )

Change subject: drivers/intel/fsp1_1: Configure UART after memory init
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Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/28464/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/28464/1//COMMIT_MSG@9 
PS1, Line 9: FSP code will default enable the onboard serial port.
           : When external serial port is used, this onboard port needs to be
           : disabled.
           : Add function mainboard_after_memory_init() function to perform
           : required actions to re-enabled output to external serial port.
> Please add a blank line between paragraphs.

Done

https://review.coreboot.org/c/coreboot/+/28464/3/src/drivers/intel/fsp1_1/ra... 
File src/drivers/intel/fsp1_1/raminit.c:

https://review.coreboot.org/c/coreboot/+/28464/3/src/drivers/intel/fsp1_1/ra... 
PS3, Line 128: mainboard_after_memory_init
> This function is used with update of Facebook FBG-1701 ( https://review.coreboot. […]

Done