[XS] Change in coreboot[main]: mb/google/brox: Fix error in DDR DQS config

[Shelley Chen (Code Review)]

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79843?usp=email )

Change subject: mb/google/brox: Fix error in DDR DQS config
......................................................................

mb/google/brox: Fix error in DDR DQS config

The DQS mapping for DIMM idx 6 was discovered to be incorrect to what
was in the schematics.  Correcting the mistake in this CL.

BUG=b:311450057,b:300690448
BRANCH=None
TEST=tested on device and it passed memory training

Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043
Signed-off-by: Shelley Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Ivy Jian 
---
M src/mainboard/google/brox/variants/baseboard/brox/memory.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified
  Ivy Jian: Looks good to me, approved

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c
index 4b03e21..05434b1 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c
@@ -53,7 +53,7 @@
    	.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
    	.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
    	.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
    	.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
    },