[XS] Change in coreboot[main]: cpu/x86/mtrr: Error out caching limitation during NEM

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81336?usp=email )

Change subject: cpu/x86/mtrr: Error out caching limitation during NEM
......................................................................

cpu/x86/mtrr: Error out caching limitation during NEM

Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.

Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).

Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
Reviewed-by: Jérémy Compostella 
---
M src/cpu/x86/mtrr/earlymtrr.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Arthur Heymans: Looks good to me, approved
  build bot (Jenkins): Verified
  Jérémy Compostella: Looks good to me, but someone else must approve

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index b6cc737..a55b2dc 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -37,6 +37,9 @@
    /* FIXME: It only support 4G less range */
    msr_t basem, maskm;

+	if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
+		printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
+			 type);
    if (!IS_POWER_OF_2(size))
    	printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
    if (size < 4 * KiB)