[L] Change in coreboot[main]: mb/intel/ptlrvp: Synchronize codebase with fatcat

[Jérémy Compostella (Code Review)]

Attention is currently required from: Bora Guvendik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/87223?usp=email )

Change subject: mb/intel/ptlrvp: Synchronize codebase with fatcat
......................................................................

Patch Set 7:

(1 comment)

File src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/87223/comment/e4eaff3a_c401f845?usp... :
PS7, Line 65: # As per document 813278, the Intel PTL-U 15W SoC supports
            : 	# Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System
            : 	# Agent (SA). The ICC Limit is represented in 1/4 A
            : 	# increments, i.e., a value of 400 = 100A.
            : 	# IA VR configuration
            : 	register "enable_fast_vmode[VR_DOMAIN_IA]" = "true"
            : 	register "cep_enable[VR_DOMAIN_IA]" = "true"
            : 	register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A
            : 	# GT VR configuration
            : 	register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
            : 	register "cep_enable[VR_DOMAIN_GT]" = "true"
            : 	register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A
            : 	# SA VR configuration
            : 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
            : 	register "cep_enable[VR_DOMAIN_SA]" = "true"
            : 	register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A
            :
> As I believe we want to support both H and U, should I remove this?

I removed this to prevent issue on PTL-H.