Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/22309
Change subject: soc/intel/denverton_ns: re-factoring hsio configuration ......................................................................
soc/intel/denverton_ns: re-factoring hsio configuration
The main goal is to allow configuring the HSIO lines from the mainboard code. Also share the code for both romstage and ramstage. Remove de explicit dependency on the harcuvar mainboard.
Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d Signed-off-by: Julien Viard de Galbert jviarddegalbert@online.net --- M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/fiamux.c M src/soc/intel/denverton_ns/include/soc/fiamux.h M src/soc/intel/denverton_ns/romstage.c 4 files changed, 10 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/22309/1
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 9547bec..813570e 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -31,8 +31,6 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> -#include <hsio.h> -#include <harcuvar_boardid.h>
static void pci_domain_set_resources(device_t dev) { @@ -74,7 +72,6 @@ { size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
@@ -82,16 +79,7 @@ supported_hsio_lanes = (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
- switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config);
if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) die("HSIO Configuration is invalid, please correct it!"); diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index 282ba03..0cee5cd 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -138,3 +138,9 @@
return fiamux_hob_data; } + +__attribute__((weak)) size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + *p_hsio_config = NULL; + return 0; +} diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h index e8aaf65..1ba57c3 100644 --- a/src/soc/intel/denverton_ns/include/soc/fiamux.h +++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h @@ -24,4 +24,6 @@ BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void); void print_fiamux_config_hob(BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data);
+size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config); + #endif // _MAINBOARD_HARCUVAR_FIAMUX_H diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 512d8cc..4403b68 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -16,8 +16,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <harcuvar_boardid.h> -#include <hsio.h> #include <reset.h> #include <soc/fiamux.h> #include <soc/iomap.h> @@ -237,7 +235,6 @@ FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config;
/* Set the parameters for MemoryInit */ @@ -250,17 +247,7 @@ /* Assume the validating silicon has max lanes. */ supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX;
- switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = - (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config);
if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config))