Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46677 )
Change subject: nb/intel/haswell/finalize.c: Use PCI register names ......................................................................
nb/intel/haswell/finalize.c: Use PCI register names
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46677/1
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..bff0344 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -5,17 +5,17 @@
void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ - pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ - pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46677 )
Change subject: nb/intel/haswell/finalize.c: Use PCI register names ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46677
to look at the new patch set (#4).
Change subject: nb/intel/haswell/finalize.c: Use PCI register names ......................................................................
nb/intel/haswell/finalize.c: Use PCI register names
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46677/4
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46677 )
Change subject: nb/intel/haswell/finalize.c: Use PCI register names ......................................................................
nb/intel/haswell/finalize.c: Use PCI register names
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46677 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 11 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..bff0344 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -5,17 +5,17 @@
void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ - pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ - pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, GGC, 1 << 0); + pci_or_config32(HOST_BRIDGE, DPR, 1 << 0); + pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10); + pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0); + pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0); + pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0); + pci_or_config32(HOST_BRIDGE, TSEG, 1 << 0); + pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */
-
Angel Pons (Code Review) -
Nico Huber (Code Review)