Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86193?usp=email )
Change subject: tree: Use true false for PcieRpLtrEnable[] ......................................................................
tree: Use true false for PcieRpLtrEnable[]
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193 Reviewed-by: Erik van den Bogaert ebogaert@eltan.com Reviewed-by: Sean Rhodes sean@starlabs.systems Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Matt DeVillier matt.devillier@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/imb-1222/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/dell/optiplex_3050/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/dedede/variants/awasuki/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/dooly/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h M util/mainboard/google/puff/template/overridetree.cb 76 files changed, 243 insertions(+), 247 deletions(-)
Approvals: Erik van den Bogaert: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, but someone else must approve
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1de7292..d0084e7 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -94,7 +94,7 @@ register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" end device ref pcie_rp4 on # Wireless controller @@ -103,7 +103,7 @@ register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" end device ref pcie_rp9 on # NVMe controller @@ -112,7 +112,7 @@ register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 996bced..e3abec8 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -253,7 +253,7 @@ # dGPU; x4 register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "0" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" @@ -262,7 +262,7 @@ # NGFF; x2 register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpMaxPayload[6]" = "RpMaxPayload_256" @@ -271,7 +271,7 @@ # LAN register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" @@ -280,7 +280,7 @@ # WLAN register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "2" register "PcieRpMaxPayload[9]" = "RpMaxPayload_256" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index d999973..cc36ce8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -117,7 +117,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "2" register "PcieRpHotPlug[4]" = "1" end @@ -127,7 +127,7 @@ # Disable CLKREQ#, since onboard LAN is always present register "PcieRpClkReqSupport[5]" = "0" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on @@ -135,7 +135,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "3" register "PcieRpHotPlug[6]" = "1" end diff --git a/src/mainboard/asrock/imb-1222/devicetree.cb b/src/mainboard/asrock/imb-1222/devicetree.cb index 4a01a5a..8edbf62 100644 --- a/src/mainboard/asrock/imb-1222/devicetree.cb +++ b/src/mainboard/asrock/imb-1222/devicetree.cb @@ -210,7 +210,7 @@ end device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" @@ -218,14 +218,14 @@ end device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[3]" = "4" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1) register "PcieRpEnable[5]" = "true" register "PcieRpSlotImplemented[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X" @@ -233,7 +233,7 @@ device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1) register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[6]" = "6" register "PcieClkSrcClkReq[6]" = "6" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/B 3042/3052 (M2_KEYB1)" "SlotDataBusWidth1X" diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 48a2bbc..749488f 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -113,7 +113,7 @@ device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" end @@ -122,7 +122,7 @@ device pci 00.0 on end end register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" @@ -130,7 +130,7 @@ end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" @@ -138,7 +138,7 @@ end device ref pcie_rp13 on register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 749cb7c..15e7064 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -71,7 +71,7 @@ register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpHotPlug[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" end device ref pcie_rp5 on @@ -80,7 +80,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN @@ -88,7 +88,7 @@ register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end device ref pcie_rp9 on @@ -97,7 +97,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb index 039709a..da11085 100644 --- a/src/mainboard/dell/optiplex_3050/devicetree.cb +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -43,7 +43,7 @@ register "PcieRpClkReqSupport[20]" = "1" register "PcieRpClkReqNumber[20]" = "3" register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieRpClkSrcNumber[20]" = "3" register "PcieRpHotPlug[20]" = "1" end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 64c9760..d87db24 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -160,7 +160,7 @@ register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "0" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" register "pcie_rp_aspm[2]" = "AspmDisabled" end @@ -170,7 +170,7 @@ register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "0" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "pcie_rp_aspm[5]" = "AspmDisabled" end @@ -181,7 +181,7 @@ register "PcieRpClkReqSupport[8]" = "0" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "pcie_rp_aspm[8]" = "AspmDisabled" end diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index bf45bcf..76b7033 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake # PCIe RP LTR configuration - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true"
# USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 791f697..9173036 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -8,7 +8,7 @@ chip soc/intel/jasperlake
# PCIe RP LTR configuration - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true"
# USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 3e1ccab..0f72b08 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -194,13 +194,13 @@
# PCIe port 9 for Card Reader register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8187868..0189e62 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -340,7 +340,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic @@ -353,7 +353,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "4" end device ref uart0 on end diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7424247..145b093 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -293,7 +293,7 @@ register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpClkSrcNumber[2]" = "0" chip drivers/net register "customized_leds" = "0x0fa5" @@ -308,7 +308,7 @@ register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieRpClkSrcNumber[3]" = "5" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" @@ -321,7 +321,7 @@ register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "1" end device ref pcie_rp9 on @@ -330,7 +330,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" chip drivers/net register "customized_leds" = "0x0fa5" @@ -343,7 +343,7 @@ register "PcieRpClkReqSupport[10]" = "1" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieRpClkSrcNumber[10]" = "2" end device ref pcie_rp12 on @@ -351,7 +351,7 @@ register "PcieRpClkReqSupport[11]" = "1" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" register "PcieRpClkSrcNumber[11]" = "2" end device ref uart0 on end diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 421ebc1..7b6de18 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -120,7 +120,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "4" end device ref pcie_rp8 on @@ -129,7 +129,7 @@ register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpClkSrcNumber[7]" = "2" end device ref pcie_rp9 on @@ -137,7 +137,7 @@ register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" end device ref pcie_rp10 off diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 54dc960..6b3eff6 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -163,7 +163,7 @@
# Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -171,7 +171,7 @@
# PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 8e7c0b0..7bc453d 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -21,7 +21,7 @@
# Enable Root port 9(x2) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -29,7 +29,7 @@
# Enable Root port 11(x2) for NVMe. register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "10" # ClkReq-to-ClkSrc mapping for CLK SRC 2 diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 27d642d..985c1af 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -72,14 +72,14 @@
# PCIe port 7 for M.2 E-key WLAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # RP 7 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3"
# Enable Root port 13 (x4) for dGPU register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "12" # ClkReq-to-ClkSrc mapping for CLK SRC 5 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index e143327..159acb3 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -315,7 +315,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW1_07" # GPP_B7 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4f5e543..8fa6a14 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -327,7 +327,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d9238b8..3a5806b 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -371,7 +371,7 @@ register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22 device pci 00.0 on end @@ -384,7 +384,7 @@ register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp9 on # x2 @@ -393,7 +393,7 @@ register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref uart0 on end device ref gspi0 on diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b3eabfd..c0c9861 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -366,7 +366,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index c1c0b20..39b4e74 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -330,7 +330,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW2_01" device pci 00.0 on end @@ -343,7 +343,7 @@ register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref gspi0 on chip drivers/spi/acpi diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 0c40c92..5cc1be7 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -319,7 +319,7 @@ register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 676b331..de3b2ab 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -309,7 +309,7 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 199a63c..9c9880f 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -185,10 +185,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 6482682..de4631a 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -163,7 +163,7 @@
# Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -171,7 +171,7 @@
# PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/google/puff/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb index 81fac90..a9a9b8e 100644 --- a/src/mainboard/google/puff/variants/dooly/overridetree.cb +++ b/src/mainboard/google/puff/variants/dooly/overridetree.cb @@ -174,7 +174,7 @@
# PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index 2db0b63..408a00b 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -246,10 +246,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 0bd90ee..eac754e 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -254,10 +254,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index ec19352..19e42ba 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -178,21 +178,21 @@
# PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -202,21 +202,21 @@
# PCIe root port 11 TPU1 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0 register "PcieRpEnable[11]" = "true" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" # RP 13 does not use a source clock request line diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 88f98ef..f0bad9d 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -246,10 +246,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index 6e6a869..9b6f020 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -178,21 +178,21 @@
# PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 5 register "PcieClkSrcUsage[5]" = "7" register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -202,21 +202,21 @@
# PCIe root port 11 TPU1 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[4]" = "10" register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0 register "PcieRpEnable[11]" = "true" - register "PcieRpLtrEnable[11]" = "1" + register "PcieRpLtrEnable[11]" = "true" # RP 11 uses CLK SRC 1 register "PcieClkSrcUsage[2]" = "11" register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "12" # RP 13 does not use a source clock request line diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 7e43c2b..61f73a0 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -169,10 +169,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 859da99..4638eee 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -179,10 +179,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 7125c40..66bf31f 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -185,21 +185,21 @@
# PCIe root port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # Uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port 9 for SSD (PCIe Lanes 9-12) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcClkReq[1]" = "1" @@ -211,14 +211,14 @@
# PCIe root port 13 TPU0 register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" # RP 13 uses CLK SRC 2 register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port 14 TPU1 register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" # RP 14 uses CLK SRC 4 register "PcieClkSrcUsage[4]" = "13" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index df25e86..a373bea7 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -180,10 +180,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index e09e861..b521763 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -188,13 +188,13 @@
# PCIe port 11 for card reader register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e0f052f..d47e183 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -183,7 +183,7 @@
# PCIe port 8 for Card Reader register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[4]" = "7" register "PcieClkSrcClkReq[4]" = "4"
@@ -199,7 +199,7 @@
# PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index ac55ac0..8110bb7 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -425,14 +425,14 @@ end device ref pcie_rp7 on # WLAN PCIE 7 using clk 1 - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "1" end device ref pcie_rp8 on # SD Card PCIE 8 using clk 3 - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" @@ -464,14 +464,14 @@ end device ref pcie_rp9 on # NVMe PCIE 9 using clk 0 - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp11 on # Optane PCIE 11 using clk 0 - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "HybridStorageMode" = "0" register "PcieRpSlotImplemented[10]" = "1" end diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 017a35d..4688c23 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -268,7 +268,7 @@ end device ref pcie_rp5 on # EMMC PCIE 5 using clk 5 - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 8267867..abf2345 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -269,7 +269,7 @@ end device ref pcie_rp5 on # EMMC PCIE 5 using clk 5 - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index afc67c6..abcc64a 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -90,13 +90,13 @@
device ref pcie_rp7 off # Disable WLAN PCIE 7 - register "PcieRpLtrEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "false" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieRpSlotImplemented[6]" = "1" end device ref pcie_rp8 off # Disable SD Card PCIE 8 - register "PcieRpLtrEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "false" register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" # override-devicetree rules say it's only diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 3b07bf7..afb564e 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -65,7 +65,7 @@ device ref pcie_rp5 on # IT8893E PCI Bridge register "PcieRpEnable[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpClkSrcNumber[4]" = "11" end @@ -73,14 +73,14 @@ # PCIe x1 slot register "PcieRpEnable[5]" = "1" register "PcieRpHotPlug[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpClkSrcNumber[5]" = "6" end device ref pcie_rp7 on # RTL8111 GbE NIC register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpClkSrcNumber[6]" = "10" end @@ -88,7 +88,7 @@ # M.2 2230 slot register "PcieRpEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieRpAdvancedErrorReporting[7]" = "1" register "PcieRpClkSrcNumber[7]" = "12" end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 70adca6..b9af2c5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -243,13 +243,13 @@ device ref pcie_rp2 off end device ref pcie_rp3 on register "PcieRpSlotImplemented[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "0x2" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp4 on register "PcieRpSlotImplemented[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -264,14 +264,14 @@ device ref pcie_rp8 off end device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "0x8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 off end device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" end device ref pcie_rp12 off end device ref uart0 off end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d1deea3..7e00917 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -245,14 +245,14 @@ device ref pcie_rp2 off end device ref pcie_rp3 on register "PcieRpSlotImplemented[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "0x2" register "PcieClkSrcClkReq[1]" = "1" end
device ref pcie_rp4 on register "PcieRpSlotImplemented[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -267,14 +267,14 @@ device ref pcie_rp8 off end device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "0x8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 off end device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" end device ref pcie_rp12 off end device ref uart0 off end diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index b923ec7..c2ac2ba 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -165,7 +165,7 @@ register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "1" register "PcieRpAdvancedErrorReporting[16]" = "1" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpClkSrcNumber[16]" = "7" register "PcieRpHotPlug[16]" = "1" end @@ -174,7 +174,7 @@ register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "11" register "PcieRpAdvancedErrorReporting[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "1" register "PcieRpHotPlug[6]" = "1" chip drivers/wifi/generic diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index e097123..cb5f211 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -172,7 +172,7 @@ device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieRpSlotImplemented[20]" = "1" register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" register "PcieRpAdvancedErrorReporting[20]" = "1" @@ -181,7 +181,7 @@ device ref pcie_rp1 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpSlotImplemented[0]" = "1" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -189,28 +189,28 @@ end device ref pcie_rp5 on # PHY 3 register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" device pci 00.0 on smbios_dev_info 3 end end device ref pcie_rp6 on # PHY 4 register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" device pci 00.0 on smbios_dev_info 4 end end device ref pcie_rp7 on # PHY 2 register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" device pci 00.0 on smbios_dev_info 2 end end device ref pcie_rp8 on # PHY 1 register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" device pci 00.0 on smbios_dev_info 1 end @@ -218,12 +218,12 @@ device ref pcie_rp9 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" end device ref pcie_rp14 on # PHY 0 register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" device pci 00.0 on smbios_dev_info 0 end @@ -233,13 +233,13 @@ device pci 00.0 on end # Aspeed 2500 VGA end register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieRpSlotImplemented[14]" = "1" end device ref pcie_rp16 on # M.2 E/CNVi # Disabled when CNVi is present register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieRpSlotImplemented[15]" = "1" end device ref uart0 on end diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index f2c75f3..7143aad 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -72,14 +72,14 @@ register "PcieRpAdvancedErrorReporting[12]" = "1"
# Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13 - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieRpLtrEnable[6]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieRpLtrEnable[9]" = "1" - register "PcieRpLtrEnable[11]" = "1" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[4]" = "true" + register "PcieRpLtrEnable[5]" = "true" + register "PcieRpLtrEnable[6]" = "true" + register "PcieRpLtrEnable[7]" = "true" + register "PcieRpLtrEnable[8]" = "true" + register "PcieRpLtrEnable[9]" = "true" + register "PcieRpLtrEnable[11]" = "true" + register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index ef1c1a9..af7fd5b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -144,49 +144,49 @@ # LAN register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "0" end device ref pcie_rp2 on # LAN register "PcieRpEnable[1]" = "true" register "PcieRpAdvancedErrorReporting[1]" = "1" - register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[1]" = "true" register "PcieRpClkSrcNumber[1]" = "1" end device ref pcie_rp3 on # LAN register "PcieRpEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieRpClkSrcNumber[2]" = "2" end device ref pcie_rp4 on # LAN register "PcieRpEnable[3]" = "true" register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "true" register "PcieRpClkSrcNumber[3]" = "3" end device ref pcie_rp5 on # LAN register "PcieRpEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "4" end device ref pcie_rp6 on # LAN register "PcieRpEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "5" end device ref pcie_rp9 on # mPCIe WIFI register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb index 9bd8e4f..e9a4d88 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb @@ -127,7 +127,7 @@ device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN) register "PcieRpEnable[6]" = "true" register "PcieRpSlotImplemented[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieRpHotPlug[6]" = "1" register "PcieClkSrcUsage[2]" = "6" register "PcieClkSrcClkReq[2]" = "2" @@ -142,7 +142,7 @@ device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe) register "PcieRpEnable[8]" = "true" register "PcieRpSlotImplemented[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" @@ -150,7 +150,7 @@ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpEnable[12]" = "true" register "PcieRpSlotImplemented[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index a043006..f4455b7 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -119,7 +119,7 @@ device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" @@ -133,7 +133,7 @@ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[1]" = "12" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index e10e41a..cd40993 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -211,20 +211,20 @@ device ref pcie_rp21 on register "PcieRpSlotImplemented[20]" = "1" register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[10]" = "20" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X" end device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieClkSrcUsage[1]" = "0x80" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end device ref pcie_rp9 on # GbE #1 register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[14]" = "8" # Type indexes are needed for systemd to use "onboard" names by default # (eno0, eno1). Otherwise it uses "slot" names that can change if any @@ -237,12 +237,12 @@ end device ref pcie_rp10 on # BMC video register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieClkSrcUsage[8]" = "9" end device ref pcie_rp11 on # GbE #2 register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[11]" = "10" device pci 00.0 on smbios_dev_info 2 diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 00b5ea6..05c619a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -158,16 +158,16 @@ device ref pcie_rp1 on end device ref pcie_rp3 on register "PcieRpEnable[2]" = "true" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index efabe95..9ab9179 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -159,7 +159,7 @@ device ref pcie_rp9 on # SSD x4 register "PcieRpSlotImplemented[8]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[1]" = "0x08" register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index a9e85ce..ed61df8 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -88,7 +88,7 @@ register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" chip drivers/wifi/generic register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" @@ -100,7 +100,7 @@ register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" register "PcieRpClkSrcNumber[8]" = "0" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device ref uart0 on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index b53a01f..d7505ef 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -45,20 +45,20 @@ device ref pcie_rp1 on # Slot JPCIE4 register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 subsystemid 0x15d9 0x1533 @@ -66,7 +66,7 @@ end device ref pcie_rp10 on register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 subsystemid 0x15d9 0x1533 @@ -74,7 +74,7 @@ end device ref pcie_rp11 on register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index f951aae..850d485 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -99,7 +99,7 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" register "PcieClkSrcClkReq[0]" = "0" @@ -107,7 +107,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 10 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[10]" = "20" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[20]" = "1" @@ -115,7 +115,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 9 (SSD1) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[8]" = "1" @@ -123,7 +123,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 5 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[5]" = "13" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[13]" = "1" @@ -131,7 +131,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 7 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[7]" = "14" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[14]" = "1" @@ -139,7 +139,7 @@ device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[15]" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index afdc264..36a9b90 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -114,21 +114,21 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 14 (SSD2) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieClkSrcUsage[14]" = "16" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 15 (SSD3) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[15]" = "20" register "PcieClkSrcClkReq[15]" = "15" end device ref pcie_rp1 on # PCI Express root port #1 x4, Clock 6 (Thunderbolt) register "PcieRpEnable[0]" = "true" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED register "PcieClkSrcClkReq[6]" = "6" @@ -136,35 +136,35 @@ device ref pcie_rp5 on # PCI Express root port #5 x4, Clock 10 (USB 3.2) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[10]" = "4" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 8 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[8]" = "8" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp13 on # PCI Express root port #13 x1, Clock 0 (WLAN) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[0]" = "12" register "PcieClkSrcClkReq[0]" = "0" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 1 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[1]" = "13" register "PcieClkSrcClkReq[1]" = "1" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 4 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[4]" = "14" register "PcieClkSrcClkReq[4]" = "4" end diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 630d669..5e70ec0 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -41,7 +41,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -49,21 +49,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index 132272d..fb902bb 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -34,7 +34,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -42,21 +42,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 7d2beab..2010b82 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -42,7 +42,7 @@ device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "true" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" register "PcieRpSlotImplemented[5]" = "1" @@ -50,7 +50,7 @@ device ref pcie_rp8 on device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" @@ -62,7 +62,7 @@ device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" @@ -71,7 +71,7 @@ device ref pcie_rp13 on device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[12]" = "1" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index d0a79806..1c5aed6 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -97,7 +97,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" register "PcieRpSlotImplemented[20]" = "1" @@ -105,7 +105,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 10 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[8]" = "1" @@ -113,7 +113,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 6 (WLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[6]" = "13" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[13]" = "1" @@ -121,7 +121,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 5 (LAN) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[5]" = "14" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[14]" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 291cb45..10a5750 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -138,7 +138,7 @@ register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" register "PcieRpHotPlug[0]" = "1" end device ref pcie_rp5 on @@ -148,7 +148,7 @@ register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" end device ref pcie_rp6 on # Root port #6 x1 (WLAN) @@ -157,7 +157,7 @@ register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" end device ref pcie_rp9 on # Root port #9 x4 (NVMe) @@ -166,7 +166,7 @@ register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6dd4eb3..a465e56 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -110,35 +110,35 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" end device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" end device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 13 (WLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[13]" = "13" register "PcieClkSrcClkReq[13]" = "13" end device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 14 (GLAN) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[14]" = "14" register "PcieClkSrcClkReq[14]" = "14" end device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 15 (Card Reader) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[15]" = "15" register "PcieClkSrcClkReq[15]" = "15" end diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index bb49da9..b1a0097 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -107,7 +107,7 @@ device ref pcie_rp17 on # PCI Express root port #17 x4, Clock 0 (Thunderbolt) register "PcieRpEnable[16]" = "true" - register "PcieRpLtrEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "true" register "PcieRpHotPlug[16]" = "1" register "PcieClkSrcUsage[0]" = "16" register "PcieClkSrcClkReq[0]" = "0" @@ -116,7 +116,7 @@ device ref pcie_rp21 on # PCI Express root port #21 x4, Clock 11 (SSD2) register "PcieRpEnable[20]" = "true" - register "PcieRpLtrEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "true" register "PcieClkSrcUsage[11]" = "20" register "PcieClkSrcClkReq[11]" = "11" register "PcieRpSlotImplemented[20]" = "1" @@ -124,7 +124,7 @@ device ref pcie_rp9 on # PCI Express root port #9 x4, Clock 12 (SSD1) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[12]" = "8" register "PcieClkSrcClkReq[12]" = "12" register "PcieRpSlotImplemented[8]" = "1" @@ -132,7 +132,7 @@ device ref pcie_rp14 on # PCI Express root port #14 x1, Clock 7 (GLAN) register "PcieRpEnable[13]" = "true" - register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "true" register "PcieClkSrcUsage[7]" = "13" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[13]" = "1" @@ -140,7 +140,7 @@ device ref pcie_rp15 on # PCI Express root port #15 x1, Clock 9 (Card Reader) register "PcieRpEnable[14]" = "true" - register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[14]" = "true" register "PcieClkSrcUsage[9]" = "14" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[14]" = "1" @@ -148,7 +148,7 @@ device ref pcie_rp16 on # PCI Express root port #16 x1, Clock 6 (WLAN) register "PcieRpEnable[15]" = "true" - register "PcieRpLtrEnable[15]" = "1" + register "PcieRpLtrEnable[15]" = "true" register "PcieClkSrcUsage[6]" = "15" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[15]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index 6ac474d..6fa540c 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -55,26 +55,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 5 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 7 (CARD) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[7]" = "6" register "PcieClkSrcClkReq[7]" = "7" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 8 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[8]" = "7" register "PcieClkSrcClkReq[8]" = "8" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 9 (SSD1) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index b4b62fa..1eab4c9 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -55,26 +55,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" #register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (CARD) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 0967154..de1e445 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -64,26 +64,26 @@ end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 10 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[10]" = "5" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index b263c5a..768f1c7 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -139,17 +139,17 @@ register "SataSalpSupport" = "1" end device ref pcie_rp1 on - register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "true" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (GLAN) - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" chip soc/intel/common/block/pcie/rtd3 @@ -161,14 +161,14 @@ end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "true" register "PcieClkSrcUsage[1]" = "7" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 4 (SSD0) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 7cfc62b..8683bb8 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -143,7 +143,7 @@ end device ref pcie_rp5 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 @@ -159,13 +159,13 @@ end device ref pcie_rp9 on # PCIe root port #9 x1, Clock 3 (CARD) - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCIe root port #10 x1, Clock 4 (GLAN) - register "PcieRpLtrEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "true" register "PcieClkSrcUsage[4]" = "9" register "PcieClkSrcClkReq[4]" = "4" chip soc/intel/common/block/pcie/rtd3 @@ -177,7 +177,7 @@ end device ref pcie_rp11 on # PCIe root port #11 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[10]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index a4e3052..45abfec 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -120,21 +120,21 @@ end device ref pcie_rp3 on # PCIe root port #3 x1, Clock 1 (WLAN) - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[2]" = "1" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 0 (SSD2) # Despite the name, SSD1_CLKREQ# is used for SSD2 - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 05f4f02..f3a7dff 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -100,7 +100,7 @@ device ref pcie_rp5 on # PCI Express Root port #5 x4, Clock 4 (TBT) register "PcieRpEnable[4]" = "true" - register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" @@ -108,21 +108,21 @@ device ref pcie_rp9 on # PCI Express Root port #9 x1, Clock 3 (LAN) register "PcieRpEnable[8]" = "true" - register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCI Express Root port #10 x1, Clock 2 (WLAN) register "PcieRpEnable[9]" = "true" - register "PcieRpLtrEnable[9]" = "0" + register "PcieRpLtrEnable[9]" = "false" register "PcieClkSrcUsage[2]" = "9" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp13 on # PCI Express Root port #13 x4, Clock 5 (NVMe) register "PcieRpEnable[12]" = "true" - register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "true" register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcClkReq[5]" = "5" end diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index ae0a514..408cdcf 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,8 +152,8 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
- /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR */ + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4e0ba86..8d5a9d1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -201,11 +201,7 @@ */ bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
- /* - * Enable/Disable Latency Tolerance Reporting for Root Port - * 0: Disable LTR - * 1: Enable LTR - */ + /* Enable/Disable Latency Tolerance Reporting for Root Port */ bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 437f015..41c7dd3c 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -277,8 +277,8 @@ /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
- /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR */ + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 7a6033a..4b33a26 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -184,10 +184,10 @@
# PCIe port 7 for LAN register "PcieRpEnable[6]" = "true" - register "PcieRpLtrEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "true" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "true" - register "PcieRpLtrEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "true" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
-
Elyes Haouas (Code Review)