Change in coreboot[master]: mc_apl3: Enable UART for GDB debugging

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36026 )

Change subject: mc_apl3: Enable UART for GDB debugging
......................................................................

mc_apl3: Enable UART for GDB debugging

Change-Id: I69dba6a8cee0b11c07b553e2960871ee5c30e8cd
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36026/1

diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c
index bd21dd1..9c992f7 100644
--- a/src/mainboard/siemens/mc_apl1/romstage.c
+++ b/src/mainboard/siemens/mc_apl1/romstage.c
@@ -145,13 +145,15 @@
 #define FPGA_TEMP_BAR0          0xf7000000
 #if CONFIG(BOARD_SIEMENS_MC_APL2)
 #define CUPER_ROOT_DEV		(PCI_DEV(0, 0x13, 0x01))
+#elif CONFIG(BOARD_SIEMENS_MC_APL3)
+#define CUPER_ROOT_DEV		(PCI_DEV(0, 0x13, 0x03))
 #endif
 #define CUPER_PCI_DEV		(PCI_DEV(FPGA_PCI_BUS, 0, 0))
 void mainboard_save_dimm_info(void)
 {
    uint32_t reg;

-	if (CONFIG(BOARD_SIEMENS_MC_APL2)) {
+	if (CONFIG(BOARD_SIEMENS_MC_APL2) || CONFIG(BOARD_SIEMENS_MC_APL3)) {
    	/* First set up root port bridge to get access to the FPGA. */
    	 /* Set secondary bus temporary. */
    	pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS,