[S] Change in coreboot[master]: soc/intel/alderlake: Allow channel 0 for memory-down

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65567 )

Change subject: soc/intel/alderlake: Allow channel 0 for memory-down
......................................................................

soc/intel/alderlake: Allow channel 0 for memory-down

Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the
System76 Lemur Pro 11 (lemp11).

Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5
Signed-off-by: Tim Crawford 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Angel Pons 
Reviewed-by: Jeremy Soller 
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 20 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Jeremy Soller: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index cbc2b5c..862a322 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -54,8 +54,8 @@
    		 * configuration.
    		 */
    		.half_channel = BIT(0),
-			/* In mixed topologies, channel 1 is always memory-down. */
-			.mixed_topo = BIT(1),
+			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
+			.mixed_topo = BIT(0) | BIT(1),
    	},
    },
    [MEM_TYPE_DDR5] = {