Change in coreboot[master]: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph.
Hello Nico Huber, Arthur Heymans, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/55213

to review the following change.

Change subject: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
......................................................................

cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR

The MSR only needs to be set when IO MWAIT redirection is to be enabled.

Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad
Signed-off-by: Angel Pons 
---
M src/cpu/intel/model_206ax/model_206ax_init.c
1 file changed, 0 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/55213/1

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index beb885e..7a40644 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -172,12 +172,6 @@
    msr.lo |= (1 << 15);	// Lock C-State MSR
    wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);

-	msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
-	msr.lo &= ~0x7ffff;
-	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
-	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
-	wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
-
    msr = rdmsr(MSR_MISC_PWR_MGMT);
    msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
    wrmsr(MSR_MISC_PWR_MGMT, msr);