Change in coreboot[master]: src/southbridge: change "unsigned" to "unsigned int" - coreboot-gerrit

25 Oct 2019

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36333 )
Change subject: src/southbridge: change "unsigned" to "unsigned int"
......................................................................
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth martin@coreboot.org
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
---
M src/southbridge/amd/amd8111/acpi.c
M src/southbridge/amd/amd8111/amd8111.c
M src/southbridge/amd/amd8111/amd8111.h
M src/southbridge/amd/amd8111/amd8111_smbus.h
M src/southbridge/amd/amd8111/early_ctrl.c
M src/southbridge/amd/amd8111/early_smbus.c
M src/southbridge/amd/amd8111/reset.c
M src/southbridge/amd/amd8132/bridge.c
M src/southbridge/broadcom/bcm5785/bcm5785.c
M src/southbridge/broadcom/bcm5785/bcm5785.h
M src/southbridge/broadcom/bcm5785/early_setup.c
M src/southbridge/broadcom/bcm5785/early_smbus.c
M src/southbridge/broadcom/bcm5785/sb_pci_main.c
M src/southbridge/broadcom/bcm5785/smbus.h
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/common/gpio.c
M src/southbridge/intel/common/gpio.h
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/gpio.h
M src/southbridge/intel/fsp_rangeley/soc.c
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82801dx/i82801dx.h
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/early_smbus.c
M src/southbridge/intel/i82801jx/i82801jx.h
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/lp_gpio.c
M src/southbridge/intel/lynxpoint/lp_gpio.h
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/nvidia/ck804/ck804.c
M src/southbridge/nvidia/ck804/ck804.h
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/early_smbus.c
M src/southbridge/nvidia/ck804/early_smbus.h
M src/southbridge/nvidia/ck804/fadt.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/ck804/sata.c
M src/southbridge/nvidia/ck804/smbus.c
M src/southbridge/nvidia/ck804/smbus.h
M src/southbridge/nvidia/mcp55/early_ctrl.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/early_smbus.c
M src/southbridge/nvidia/mcp55/fadt.c
M src/southbridge/nvidia/mcp55/mcp55.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/nic.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/southbridge/nvidia/mcp55/smbus.h
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
67 files changed, 256 insertions(+), 256 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36333/1

diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index ab48833..a735ff9 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -100,7 +100,7 @@
#if CONFIG(HAVE_ACPI_TABLES)
-unsigned pm_base;
+unsigned int pm_base;
 #endif
static void acpi_init(struct device *dev)
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index cbf0d3085..0180f45 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -21,15 +21,15 @@
 {
    struct device *lpc_dev;
    struct device *bus_dev;
-	unsigned index;
-	unsigned reg_old, reg;
+	unsigned int index;
+	unsigned int reg_old, reg;
/* See if we are on the bus behind the amd8111 pci bridge */
    bus_dev = dev->bus->dev;
    if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
        (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
    {
-		unsigned devfn;
+		unsigned int devfn;
    	devfn = bus_dev->path.pci.devfn + (1 << 3);
    	lpc_dev = pcidev_path_behind(bus_dev->bus, devfn);
    	index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
@@ -37,7 +37,7 @@
    		index = 16;
    	}
    } else {
-		unsigned devfn;
+		unsigned int devfn;
    	devfn = (dev->path.pci.devfn) & ~7;
    	lpc_dev = pcidev_path_behind(dev->bus, devfn);
    	index = dev->path.pci.devfn & 7;
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
index 447edf9..fc57936 100644
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ b/src/southbridge/amd/amd8111/amd8111.h
@@ -17,6 +17,6 @@
 #include <device/device.h>
void amd8111_enable(struct device *dev);
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
#endif /* AMD8111_H */
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index 7386965..894fcd0 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -29,7 +29,7 @@
    outb(0x80, 0x80);
 }
-static int smbus_wait_until_ready(unsigned smbus_io_base)
+static int smbus_wait_until_ready(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -48,7 +48,7 @@
    return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
-static int smbus_wait_until_done(unsigned smbus_io_base)
+static int smbus_wait_until_done(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -64,10 +64,10 @@
    return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device)
+static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
 {
-	unsigned global_status_register;
-	unsigned byte;
+	unsigned int global_status_register;
+	unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
    	return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -110,10 +110,10 @@
    return byte;
 }
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device,
-			      unsigned value)
+static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
+			      unsigned int value)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
    	return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -153,11 +153,11 @@
 }
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device,
+static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
    		      unsigned int address)
 {
-	unsigned global_status_register;
-	unsigned byte;
+	unsigned int global_status_register;
+	unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
    	return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -200,10 +200,10 @@
    return byte;
 }
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device,
+static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
    		       unsigned int address, unsigned char val)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
    	return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -239,11 +239,11 @@
    return 0;
 }
-static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device,
-			       unsigned cmd, u8 bytes, u8 *buf)
+static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device,
+			       unsigned int cmd, u8 bytes, u8 *buf)
 {
-	unsigned global_status_register;
-	unsigned i;
+	unsigned int global_status_register;
+	unsigned int i;
    u8 msglen;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
@@ -296,11 +296,11 @@
    return i;
 }
-static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device,
-				unsigned cmd, u8 bytes, const u8 *buf)
+static int do_smbus_block_write(unsigned int smbus_io_base, unsigned int device,
+				unsigned int cmd, u8 bytes, const u8 *buf)
 {
-	unsigned global_status_register;
-	unsigned i;
+	unsigned int global_status_register;
+	unsigned int i;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
    	return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index 8b12d83..e9676eb 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -19,7 +19,7 @@
 #include <southbridge/amd/common/reset.h>
 #include "amd8111.h"
-unsigned get_sbdn(unsigned bus)
+unsigned int get_sbdn(unsigned int bus)
 {
    pci_devfn_t dev;
@@ -34,7 +34,7 @@
}
-static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
+static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn)
 {
    pci_devfn_t dev;
    uint8_t byte;
@@ -48,9 +48,9 @@
static void enable_cf9(void)
 {
-	unsigned sblk = get_sblk();
-	unsigned sbbusn = get_sbbusn(sblk);
-	unsigned sbdn = get_sbdn(sbbusn);
+	unsigned int sblk = get_sblk();
+	unsigned int sbbusn = get_sbbusn(sblk);
+	unsigned int sbdn = get_sbdn(sbbusn);
enable_cf9_x(sbbusn, sbdn);
 }
@@ -63,7 +63,7 @@
    outb(0x0e, 0x0cf9); // make sure cf9 is enabled
 }
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
 {
    pci_devfn_t dev;
@@ -76,7 +76,7 @@
}
-static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
+static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn)
 {
    pci_devfn_t dev;
@@ -91,9 +91,9 @@
 void do_soft_reset(void)
 {
-	unsigned sblk = get_sblk();
-	unsigned sbbusn = get_sbbusn(sblk);
-	unsigned sbdn = get_sbdn(sbbusn);
+	unsigned int sblk = get_sblk();
+	unsigned int sbbusn = get_sbbusn(sblk);
+	unsigned int sbdn = get_sbdn(sbbusn);
return soft_reset_x(sbbusn, sbdn);
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
index cabb31b..c821902 100644
--- a/src/southbridge/amd/amd8111/early_smbus.c
+++ b/src/southbridge/amd/amd8111/early_smbus.c
@@ -64,13 +64,13 @@
    return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }
-static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes,
+static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes,
    			   u8 *buf)
 {
    return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
 }
-static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes,
+static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
    			    const u8 *buf)
 {
    return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index f4907c5..b175be2 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -21,7 +21,7 @@
#define PCI_DEV_INVALID (0xffffffffU)
-static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
 {
    pci_devfn_t dev, last;
    dev = PCI_DEV(bus, 0, 0);
@@ -41,9 +41,9 @@
 void do_board_reset(void)
 {
    pci_devfn_t dev;
-	unsigned bus;
-	unsigned node = 0;
-	unsigned link = get_sblk();
+	unsigned int bus;
+	unsigned int node = 0;
+	unsigned int link = get_sblk();
/* Find the device.
     * There can only be one 8111 on a hypertransport chain/bus.
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 527a736..1088dda 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -43,8 +43,8 @@
 }
struct amd8132_bus_info {
-	unsigned sstatus;
-	unsigned rev;
+	unsigned int sstatus;
+	unsigned int rev;
    int master_devices;
    int max_func;
 };
@@ -65,9 +65,9 @@
 static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
 {
    struct amd8132_bus_info *info = ptr;
-	unsigned cap;
-	unsigned status, cmd, orig_cmd;
-	unsigned max_read, max_tran;
+	unsigned int cap;
+	unsigned int status, cmd, orig_cmd;
+	unsigned int max_read, max_tran;
    int  sibs;
if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
@@ -133,10 +133,10 @@
}
 static void amd8132_scan_bus(struct bus *bus,
-	unsigned min_devfn, unsigned max_devfn)
+	unsigned int min_devfn, unsigned int max_devfn)
 {
    struct amd8132_bus_info info;
-	unsigned pos;
+	unsigned int pos;
/* Find the children on the bus */
    pci_scan_bus(bus, min_devfn, max_devfn);
@@ -162,7 +162,7 @@
     */
    if (!bus->children)
    {
-		unsigned pcix_misc;
+		unsigned int pcix_misc;
    	/* Disable all of my children */
    	disable_children(bus);
@@ -198,7 +198,7 @@
 {
    uint32_t dword;
    uint8_t byte;
-	unsigned chip_rev;
+	unsigned int chip_rev;
/* Find the revision of the 8132 */
    chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
@@ -368,7 +368,7 @@
 static void amd8132_ioapic_init(struct device *dev)
 {
    uint32_t dword;
-	unsigned chip_rev;
+	unsigned int chip_rev;
/* Find the revision of the 8132 */
    chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 50d13b0..ea77359 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -31,21 +31,21 @@
    if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
    	(bus_dev->device == 0x0036)) // device under PCI-X Bridge
    {
-		unsigned devfn;
+		unsigned int devfn;
    	devfn = bus_dev->path.pci.devfn + (1 << 3);
    	sb_pci_main_dev = pcidev_path_behind(bus_dev->bus, devfn);
    	// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
    } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
    	(bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X)
    {
-		unsigned devfn;
+		unsigned int devfn;
    	devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
    	sb_pci_main_dev = pcidev_path_behind(bus_dev->bus->dev->bus,
    					devfn);
    	// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
    }
    else { // same bus
-		unsigned devfn;
+		unsigned int devfn;
    	devfn = (dev->path.pci.devfn) & ~7;
    	if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) {
    		if (dev->device == 0x0036) //PCI-X Bridge
@@ -62,7 +62,7 @@
// get index now
 #if 0
-	unsigned reg_old, reg;
+	unsigned int reg_old, reg;
    if (index < 16) {
    	reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48);
    	reg &= ~(1 << index);
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index e1c6f66..db723dd 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -21,7 +21,7 @@
 #include "chip.h"
void bcm5785_enable(struct device *dev);
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
    		       unsigned int device);
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 8ea776f7..b4d623b 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -64,7 +64,7 @@
    pci_write_config8(dev, 0x40, 1 << 2);
 }
-unsigned get_sbdn(unsigned bus)
+unsigned int get_sbdn(unsigned int bus)
 {
    pci_devfn_t dev;
@@ -81,7 +81,7 @@
#define SB_VFSMAF 0
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
 {
    //ACPI Decode Enable
    outb(0x0e, 0xcd6);
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 5aa6ee2..05e401d 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -40,22 +40,22 @@
    outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
-static inline int smbus_recv_byte(unsigned device)
+static inline int smbus_recv_byte(unsigned int device)
 {
    return do_smbus_recv_byte(SMBUS_IO_BASE, device);
 }
-static inline int smbus_send_byte(unsigned device, unsigned char val)
+static inline int smbus_send_byte(unsigned int device, unsigned char val)
 {
    return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
 }
-static inline int smbus_read_byte(unsigned device, unsigned address)
+static inline int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static inline int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val)
 {
    return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 318086e..837ce42 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -72,7 +72,7 @@
static int lsmbus_recv_byte(struct device *dev)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -86,7 +86,7 @@
static int lsmbus_send_byte(struct device *dev, uint8_t val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -100,7 +100,7 @@
static int lsmbus_read_byte(struct device *dev, uint8_t address)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -114,7 +114,7 @@
static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index 657d97d..40ed774 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -42,7 +42,7 @@
    outb(0x80, 0x80);
 }
-static int smbus_wait_until_ready(unsigned smbus_io_base)
+static int smbus_wait_until_ready(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -58,7 +58,7 @@
    return -2; // time out
 }
-static int smbus_wait_until_done(unsigned smbus_io_base)
+static int smbus_wait_until_done(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -78,7 +78,7 @@
    return -3; // timeout
 }
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
 {
    uint8_t byte;
@@ -105,7 +105,7 @@
    return byte;
 }
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
 {
    uint8_t byte;
@@ -132,7 +132,7 @@
    return 0;
 }
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
 {
    uint8_t byte;
@@ -162,7 +162,7 @@
    return byte;
 }
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
 {
    uint8_t byte;
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index d3847a5..f570040 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -51,7 +51,7 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1670091..ea60085 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -154,7 +154,7 @@
 static int mei_wait_for_me_ready(void)
 {
    struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
while (try--) {
    	read_me_csr(&me);
@@ -195,7 +195,7 @@
    		void *req_data)
 {
    struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
    u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -260,8 +260,8 @@
    struct mei_header mei_rsp;
    struct mkhi_header mkhi_rsp;
    struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
    u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 9543536..54c3fff 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -156,7 +156,7 @@
 static int mei_wait_for_me_ready(void)
 {
    struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
while (try--) {
    	read_me_csr(&me);
@@ -197,7 +197,7 @@
    		void *req_data)
 {
    struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
    u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -262,8 +262,8 @@
    struct mei_header mei_rsp;
    struct mkhi_header mkhi_rsp;
    struct mei_csr me, host;
-	unsigned ndata, n/*, me_data_len*/;
-	unsigned expected;
+	unsigned int ndata, n/*, me_data_len*/;
+	unsigned int expected;
    u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 475def3..de7fc36 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -87,7 +87,7 @@
 #define IOBP_RETRY 1000
 static inline int iobp_poll(void)
 {
-	unsigned try = IOBP_RETRY;
+	unsigned int try = IOBP_RETRY;
    u32 data;
while (try--) {
@@ -147,7 +147,7 @@
#ifndef __SMM__
 /* Set bit in function disable register to hide this device */
-static void pch_hide_devfn(unsigned devfn)
+static void pch_hide_devfn(unsigned int devfn)
 {
    switch (devfn) {
    case PCI_DEVFN(20, 0): /* xHCI */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 22b9107..ac976c2 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,7 +66,7 @@
 void enable_usb_bar(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
void early_thermal_init(void);
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 2c2f9d9..98a4bdb 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,8 +74,8 @@
    printk(BIOS_DEBUG, "done.\n");
 }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
    u8 access_cntl;
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 0245f4f..0669b5f 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -124,11 +124,11 @@
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
 {
    int gpio;
-	unsigned bitmask = 1;
-	unsigned vector = 0;
+	unsigned int bitmask = 1;
+	unsigned int vector = 0;
while (bitmask &&
           ((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 019009e..eba2d01 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -172,7 +172,7 @@
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 73181cf..14b3a09 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -102,7 +102,7 @@
    uint16_t *optype;
    uint32_t *addr;
    uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
    uint8_t *status;
    uint16_t *control;
    uint32_t *bbar;
@@ -169,7 +169,7 @@
    u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -178,7 +178,7 @@
    u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -187,7 +187,7 @@
    u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -195,21 +195,21 @@
 {
    write8(addr, b);
    printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
static void writew_(u16 b, void *addr)
 {
    write16(addr, b);
    printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
static void writel_(u32 b, void *addr)
 {
    write32(addr, b);
    printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
@@ -367,13 +367,13 @@
    uint32_t offset;
 } spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
    trans->out += bytes;
    trans->bytesout -= bytes;
 }
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
    trans->in += bytes;
    trans->bytesin -= bytes;
@@ -801,8 +801,8 @@
    if (addr + len > flash->size) {
    	printk(BIOS_ERR,
    		"Attempt to read %x-%x which is out of chip\n",
-			(unsigned) addr,
-			(unsigned) addr+(unsigned) len);
+			(unsigned int) addr,
+			(unsigned intint) addr+(unsigned) len);
    	return -1;
    }
@@ -872,7 +872,7 @@
    if (addr + len > flash->size) {
    	printk(BIOS_ERR,
    		"Attempt to write 0x%x-0x%x which is out of chip\n",
-			(unsigned)addr, (unsigned) (addr+len));
+			(unsigned intint)addr, (unsigned) (addr+len));
    	return -1;
    }
@@ -906,7 +906,7 @@
    	len -= block_len;
    }
    printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
-	       (unsigned) (addr - start), start);
+	       (unsigned int) (addr - start), start);
    return 0;
 }
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 48b7769..da0c54b 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -51,7 +51,7 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 1a916f4..6a27fea 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -119,6 +119,6 @@
  * Get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of GPIO pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index ec66c43..3512f19 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -59,7 +59,7 @@
 }
/* Set bit in Function Disable register to hide this device */
-static void soc_hide_devfn(unsigned devfn)
+static void soc_hide_devfn(unsigned int devfn)
 {
 /* TODO Function Disable. */
 }
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index d2f2a0b..f58677b 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -121,7 +121,7 @@
    uint16_t *optype;
    uint32_t *addr;
    uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
    uint8_t *status;
    uint16_t *control;
    uint32_t *bbar;
@@ -199,7 +199,7 @@
 {
    u8 v = read8(addr);
    printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -207,7 +207,7 @@
 {
    u16 v = read16(addr);
    printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -215,7 +215,7 @@
 {
    u32 v = read32(addr);
    printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
    return v;
 }
@@ -223,21 +223,21 @@
 {
    write8(addr, b);
    printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
static void writew_(u16 b, const void *addr)
 {
    write16(addr, b);
    printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
static void writel_(u32 b, const void *addr)
 {
    write32((unsigned long)addr, b);
    printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
@@ -397,13 +397,13 @@
    uint32_t offset;
 } spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
    trans->out += bytes;
    trans->bytesout -= bytes;
 }
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
    trans->in += bytes;
    trans->bytesin -= bytes;
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 9aa3017..50122d8 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -36,7 +36,7 @@
void i82801dx_enable(struct device *dev);
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 void aseg_smm_lock(void);
#endif
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 6949a30..54ad3c3 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -52,7 +52,7 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 341a98a..132b684 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -137,7 +137,7 @@
    				   (1 << 29) | (1 << 17) | (2 << 2));
 }
-static int i82801ix_function_disabled(const unsigned devfn)
+static int i82801ix_function_disabled(const unsigned int devfn)
 {
    struct device *const dev = pcidev_path_on_root(devfn);
    if (!dev) {
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 7c4faf0..906d24e 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -215,7 +215,7 @@
 void i82801ix_dmi_poll_vc1(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
#endif
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index f7d8b87..47254f9 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -34,8 +34,8 @@
    printk(BIOS_DEBUG, "done.\n");
 }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
    u8 access_cntl;
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index d2b87d1..adba27c 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -47,7 +47,7 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 28c9f68..7b88218 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -227,7 +227,7 @@
#if ENV_ROMSTAGE
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
    	u8 *buf);
 int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index a4f5a01..a24685a 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -34,8 +34,8 @@
    printk(BIOS_DEBUG, "done.\n");
 }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
    u8 access_cntl;
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 241584b..bd130c0 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -51,22 +51,22 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-int smbus_write_byte(unsigned device, unsigned address, u8 data)
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
 {
   return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
 }
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
 {
    return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
 }
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
 {
    return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
 }
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 8d3ae02..f804126 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -155,7 +155,7 @@
 static int mei_wait_for_me_ready(void)
 {
    struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
while (try--) {
    	read_me_csr(&me);
@@ -196,7 +196,7 @@
    		void *req_data)
 {
    struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
    u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -261,8 +261,8 @@
    struct mei_header mei_rsp;
    struct mkhi_header mkhi_rsp;
    struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
    u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 9e5fa24..9ee76f2 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -56,10 +56,10 @@
 void enable_usb_bar(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
-int smbus_write_byte(unsigned device, unsigned address, u8 data);
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+int smbus_read_byte(unsigned int device, unsigned int address);
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
 #endif
void early_pch_init(void);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 95cac81..d31fd70 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -68,8 +68,8 @@
    printk(BIOS_DEBUG, "done.\n");
 }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
    u8 access_cntl;
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index d3847a5..f570040 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -51,7 +51,7 @@
    printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index bc8d8a1..1919d58 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -127,11 +127,11 @@
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
 {
    int gpio;
-	unsigned bitmask = 1;
-	unsigned vector = 0;
+	unsigned int bitmask = 1;
+	unsigned int vector = 0;
while (bitmask &&
           ((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fa6d700..8436243 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -169,7 +169,7 @@
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 8d86e68..425e7f1 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -161,7 +161,7 @@
 static int mei_wait_for_me_ready(void)
 {
    struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
while (try--) {
    	read_me_csr(&me);
@@ -201,7 +201,7 @@
 static int mei_send_packet(struct mei_header *mei, void *req_data)
 {
    struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
    u32 *data;
/* Number of dwords to write */
@@ -305,8 +305,8 @@
 {
    struct mei_header mei_rsp;
    struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
    u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index a57bae3..dc7b958 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -197,7 +197,7 @@
 #define IOBP_RETRY 1000
 static inline int iobp_poll(void)
 {
-	unsigned try;
+	unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
    	u16 status = RCBA16(IOBPS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index be4285b..d83dd17 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -177,7 +177,7 @@
 void enable_smbus(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 1eb8e4b..92dd02e 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -168,7 +168,7 @@
 static void pch_pcie_device_set_func(int index, int pci_func)
 {
    struct device *dev;
-	unsigned new_devfn;
+	unsigned int new_devfn;
dev = rpc.ports[index];
diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c
index 02d70a6..2293392 100644
--- a/src/southbridge/nvidia/ck804/ck804.c
+++ b/src/southbridge/nvidia/ck804/ck804.c
@@ -22,7 +22,7 @@
static u32 final_reg;
-static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
+static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
 {
    struct device *lpc_dev;
@@ -54,7 +54,7 @@
 static void ck804_enable(struct device *dev)
 {
    struct device *lpc_dev;
-	unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
+	unsigned int index = 0, index2 = 0, deviceid, vendorid, devfn;
    u32 reg_old, reg;
    u8 byte;
@@ -179,8 +179,8 @@
    }
 }
-static void ck804_set_subsystem(struct device *dev, unsigned vendor,
-				unsigned device)
+static void ck804_set_subsystem(struct device *dev, unsigned int vendor,
+				unsigned int device)
 {
    pci_write_config32(dev, 0x40,
    		   ((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index 6812b5b..c4c4c4f 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -26,6 +26,6 @@
 #define CK804B_BUSN 0x80
 #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
#endif
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index d981b7e..bbd8210 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -24,20 +24,20 @@
 #include "ck804.h"
/* Someone messed up and snuck in some K8-specific code */
-static int  set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
+static int  set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid, unsigned int val) { return 0; /* stub */};
static int set_ht_link_ck804(u8 ht_c_num)
 {
-	unsigned vendorid = 0x10de;
-	unsigned val = 0x01610169;
+	unsigned int vendorid = 0x10de;
+	unsigned int val = 0x01610169;
    return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
-static void setup_ss_table(unsigned index, unsigned where, unsigned control,
+static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
    		   const unsigned int *register_values, int max)
 {
    int i;
-	unsigned val;
+	unsigned int val;
val = inl(control);
    val &= 0xfffffffe;
@@ -77,8 +77,8 @@
  */
 #define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r)
-static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
-				 unsigned *io_base)
+static void ck804_early_set_port(unsigned int ck804_num, unsigned int *busn,
+				 unsigned int *io_base)
 {
    static const unsigned int ctrl_devport_conf[] = {
    	CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
@@ -97,8 +97,8 @@
    }
 }
-static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
-				   unsigned *io_base)
+static void ck804_early_clear_port(unsigned int ck804_num, unsigned int *busn,
+				   unsigned int *io_base)
 {
    static const unsigned int ctrl_devport_conf_clear[] = {
    	CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0,
@@ -117,8 +117,8 @@
    }
 }
-static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
-			      unsigned *io_base)
+static void ck804_early_setup(unsigned int ck804_num, unsigned int *busn,
+			      unsigned int *io_base)
 {
    static const unsigned int ctrl_conf_master[] = {
    	RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880,
@@ -337,7 +337,7 @@
static int ck804_early_setup_x(void)
 {
-	unsigned busn[4], io_base[4];
+	unsigned int busn[4], io_base[4];
    int i, ck804_num = 0;
for (i = 0; i < 4; i++) {
@@ -380,7 +380,7 @@
    outb(0x06, 0x0cf9);
 }
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
 {
    /* The default value for CK804 is good. */
    /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c
index a310422..8997ef0 100644
--- a/src/southbridge/nvidia/ck804/early_smbus.c
+++ b/src/southbridge/nvidia/ck804/early_smbus.c
@@ -55,23 +55,23 @@
    printk(BIOS_DEBUG, "SMBus controller enabled\n");
 }
-int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address)
+int ck804_smbus_read_byte(unsigned int bus, unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS_BASE(bus), device, address);
 }
-int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address,
+int ck804_smbus_write_byte(unsigned int bus, unsigned int device, unsigned int address,
    		   unsigned char val)
 {
    return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val);
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return ck804_smbus_read_byte(0, device, address);
 }
-int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val)
 {
    return ck804_smbus_write_byte(0, device, address, val);
 }
diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h
index 5aacd93..774e38c 100644
--- a/src/southbridge/nvidia/ck804/early_smbus.h
+++ b/src/southbridge/nvidia/ck804/early_smbus.h
@@ -11,7 +11,7 @@
  * GNU General Public License for more details.
  */
-int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned);
+int ck804_smbus_read_byte(unsigned intint, unsigned int, unsigned);
 int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char);
 void enable_smbus(void);
 int smbus_read_byte(unsigned int, unsigned int);
diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c
index 713a51e..55f98bf 100644
--- a/src/southbridge/nvidia/ck804/fadt.c
+++ b/src/southbridge/nvidia/ck804/fadt.c
@@ -22,7 +22,7 @@
 #include <arch/acpi.h>
 #include <version.h>
-extern unsigned pm_base;	/* pm_base should be set in sb acpi */
+extern unsigned int pm_base;	/* pm_base should be set in sb acpi */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 63e0de5..b8aec26 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -97,7 +97,7 @@
    	pci_write_config8(dev, 0x6d, new);
 }
-unsigned pm_base = 0;
+unsigned int pm_base = 0;
static void lpc_init(struct device *dev)
 {
diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c
index c5dc56e..9abd6d2 100644
--- a/src/southbridge/nvidia/ck804/sata.c
+++ b/src/southbridge/nvidia/ck804/sata.c
@@ -27,7 +27,7 @@
 #endif
#if CK804_SATA_RESET_FOR_ATAPI
-static void sata_com_reset(struct device *dev, unsigned reset)
+static void sata_com_reset(struct device *dev, unsigned int reset)
 // reset = 1 : reset
 // reset = 0 : clear
 {
diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c
index b96dc6e..9737d00 100644
--- a/src/southbridge/nvidia/ck804/smbus.c
+++ b/src/southbridge/nvidia/ck804/smbus.c
@@ -23,7 +23,7 @@
static int lsmbus_recv_byte(struct device *dev)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -37,7 +37,7 @@
static int lsmbus_send_byte(struct device *dev, u8 val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -51,7 +51,7 @@
static int lsmbus_read_byte(struct device *dev, u8 address)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -65,7 +65,7 @@
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index bf0ff3c..9aad5e1 100644
--- a/src/southbridge/nvidia/ck804/smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
@@ -35,7 +35,7 @@
    outb(0x80, 0x80);
 }
-static int smbus_wait_until_done(unsigned smbus_io_base)
+static int smbus_wait_until_done(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -52,7 +52,7 @@
/* Platform has severe issues placing non-inlined functions in headers. */
 #if ENV_RAMSTAGE
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
 {
    unsigned char global_status_register, byte;
@@ -85,10 +85,10 @@
    return byte;
 }
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
+static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
    		      unsigned char val)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
    smbus_delay();
@@ -118,8 +118,8 @@
 }
 #endif /* ENV_RAMSTAGE */
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
-			      unsigned address)
+static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
+			      unsigned int address)
 {
    unsigned char global_status_register, byte;
@@ -152,10 +152,10 @@
    return byte;
 }
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
-			       unsigned address, unsigned char val)
+static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
+			       unsigned int address, unsigned char val)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
    smbus_delay();
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 092280b..042dfa0 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -38,7 +38,7 @@
    outb(0x0e, 0x0cf9);
 }
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
 {
    /* The default value for MCP55 is good. */
    /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 69d12bf..85198ad 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -21,21 +21,21 @@
 #include <device/pci_ops.h>
#ifdef UNUSED_CODE
-int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
+int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val);
static int set_ht_link_mcp55(u8 ht_c_num)
 {
-	unsigned vendorid = 0x10de;
-	unsigned val = 0x01610109;
+	unsigned int vendorid = 0x10de;
+	unsigned int val = 0x01610109;
    /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
    return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
-static void setup_ss_table(unsigned index, unsigned where, unsigned control,
+static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
    		   const unsigned int *register_values, int max)
 {
    int i;
-	unsigned val;
+	unsigned int val;
val = inl(control);
    val &= 0xfffffffe;
@@ -82,8 +82,8 @@
  */
 #define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r)
-static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
-				 unsigned *devn, unsigned *io_base)
+static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn,
+				 unsigned int *devn, unsigned int *io_base)
 {
static const unsigned int ctrl_devport_conf[] = {
@@ -100,8 +100,8 @@
    }
 }
-static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
-				   unsigned *devn, unsigned *io_base)
+static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn,
+				   unsigned int *devn, unsigned int *io_base)
 {
    static const unsigned int ctrl_devport_conf_clear[] = {
    	MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
@@ -117,8 +117,8 @@
    }
 }
-static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
-				   unsigned anactrl_io_base, unsigned pci_e_x)
+static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx,
+				   unsigned int anactrl_io_base, unsigned int pci_e_x)
 {
    u32 tgio_ctrl, pll_ctrl, dword;
    int i;
@@ -156,9 +156,9 @@
    mdelay(100); /* Need to wait 100ms. */
 }
-static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
-			      unsigned *devn, unsigned *io_base,
-			      unsigned *pci_e_x)
+static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn,
+			      unsigned int *devn, unsigned int *io_base,
+			      unsigned int *pci_e_x)
 {
     static const unsigned int ctrl_conf_1[] = {
    RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
@@ -348,21 +348,21 @@
 static int mcp55_early_setup_x(void)
 {
    /* Find out how many MCP55 we have. */
-	unsigned busn[HT_CHAIN_NUM_MAX] = {0};
-	unsigned devn[HT_CHAIN_NUM_MAX] = {0};
-	unsigned io_base[HT_CHAIN_NUM_MAX] = {0};
+	unsigned int busn[HT_CHAIN_NUM_MAX] = {0};
+	unsigned int devn[HT_CHAIN_NUM_MAX] = {0};
+	unsigned int io_base[HT_CHAIN_NUM_MAX] = {0};
/*
     * FIXME: May have problem if there is different MCP55 HTX card with
     * different PCI_E lane allocation. Need to use same trick about
     * pci1234 to verify node/link connection.
     */
-	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {
+	unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = {
    	CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
    	CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
    };
    int mcp55_num = 0, ht_c_index;
-	unsigned busnx, devnx;
+	unsigned int busnx, devnx;
/* FIXME: Multi PCI segment handling. */
diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c
index fe9ccdd..1b49456 100644
--- a/src/southbridge/nvidia/mcp55/early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/early_smbus.c
@@ -48,48 +48,48 @@
    outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
 }
-int smbus_recv_byte(unsigned device)
+int smbus_recv_byte(unsigned int device)
 {
    return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
 }
-int smbus_send_byte(unsigned device, unsigned char val)
+int smbus_send_byte(unsigned int device, unsigned char val)
 {
    return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
 }
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
    return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
 }
-int smbus_write_byte(unsigned device, unsigned address,
+int smbus_write_byte(unsigned int device, unsigned int address,
    			   unsigned char val)
 {
    return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
 }
-int smbusx_recv_byte(unsigned smb_index, unsigned device)
+int smbusx_recv_byte(unsigned int smb_index, unsigned int device)
 {
    return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
 }
-int smbusx_send_byte(unsigned smb_index, unsigned device,
+int smbusx_send_byte(unsigned int smb_index, unsigned int device,
    			   unsigned char val)
 {
    return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
    			  device, val);
 }
-int smbusx_read_byte(unsigned smb_index, unsigned device,
-				   unsigned address)
+int smbusx_read_byte(unsigned int smb_index, unsigned int device,
+				   unsigned int address)
 {
    return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
    			  device, address);
 }
-int smbusx_write_byte(unsigned smb_index, unsigned device,
-				    unsigned address, unsigned char val)
+int smbusx_write_byte(unsigned int smb_index, unsigned int device,
+				    unsigned int address, unsigned char val)
 {
    return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
    			   device, address, val);
diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c
index 9a70ba1..16f0df8 100644
--- a/src/southbridge/nvidia/mcp55/fadt.c
+++ b/src/southbridge/nvidia/mcp55/fadt.c
@@ -23,7 +23,7 @@
 #include <device/pci_ids.h>
 #include <version.h>
-extern unsigned pm_base;
+extern unsigned int pm_base;
/* Create the Fixed ACPI Description Tables (FADT) for this board. */
 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c
index bd49d9b..db646cd 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.c
+++ b/src/southbridge/nvidia/mcp55/mcp55.c
@@ -25,7 +25,7 @@
static u32 final_reg;
-static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
+static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
 {
    struct device *lpc_dev;
@@ -55,10 +55,10 @@
 void mcp55_enable(struct device *dev)
 {
    struct device *lpc_dev = NULL, *sm_dev = NULL;
-	unsigned index = 0, index2 = 0;
+	unsigned int index = 0, index2 = 0;
    u32 reg_old, reg;
    u8 byte;
-	unsigned deviceid, vendorid, devfn;
+	unsigned int deviceid, vendorid, devfn;
    int i;
if (dev->device == 0x0000) {
@@ -217,8 +217,8 @@
    }
 }
-static void mcp55_set_subsystem(struct device *dev, unsigned vendor,
-				unsigned device)
+static void mcp55_set_subsystem(struct device *dev, unsigned int vendor,
+				unsigned int device)
 {
    pci_write_config32(dev, 0x40,
    		   ((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index ac68909..c3e93d3 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -30,19 +30,19 @@
 extern struct pci_operations mcp55_pci_ops;
 #endif
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
 void enable_smbus(void);
/* Concflict declarations with <device/smbus.h>. */
 #if !ENV_RAMSTAGE
-int smbus_recv_byte(unsigned device);
-int smbus_send_byte(unsigned device, unsigned char val);
-int smbus_read_byte(unsigned device, unsigned address);
-int smbus_write_byte(unsigned device, unsigned address, unsigned char val);
-int smbusx_recv_byte(unsigned smb_index, unsigned device);
-int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val);
-int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
-int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
+int smbus_recv_byte(unsigned int device);
+int smbus_send_byte(unsigned int device, unsigned char val);
+int smbus_read_byte(unsigned int device, unsigned int address);
+int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val);
+int smbusx_recv_byte(unsigned int smb_index, unsigned int device);
+int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val);
+int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address);
+int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address,
    	unsigned char val);
 #endif /* !ENV_RAMSTAGE */
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index af4df44..9e350dd 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -29,10 +29,10 @@
 #include "chip.h"
 #include "mcp55.h"
-static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg)
 {
    u32 dword;
-	unsigned loop = 0x100;
+	unsigned int loop = 0x100;
write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
    mdelay(1);
@@ -61,7 +61,7 @@
 {
    u32 dword;
    int i, val;
-	unsigned id;
+	unsigned int id;
dword = read32(base + 0x188);
    dword &= ~(1 << 20);
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 37f4a1e..0f8dbe3 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -26,7 +26,7 @@
static int lsmbus_recv_byte(struct device *dev)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -40,7 +40,7 @@
static int lsmbus_send_byte(struct device *dev, u8 val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -54,7 +54,7 @@
static int lsmbus_read_byte(struct device *dev, u8 address)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -68,7 +68,7 @@
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
 {
-	unsigned device;
+	unsigned int device;
    struct resource *res;
    struct bus *pbus;
@@ -87,7 +87,7 @@
 };
#if CONFIG(HAVE_ACPI_TABLES)
-unsigned pm_base;
+unsigned int pm_base;
 #endif
static void mcp55_sm_read_resources(struct device *dev)
diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index f270452..91e48ba 100644
--- a/src/southbridge/nvidia/mcp55/smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
@@ -37,7 +37,7 @@
    outb(0x80, 0x80);
 }
-static int smbus_wait_until_done(unsigned smbus_io_base)
+static int smbus_wait_until_done(unsigned int smbus_io_base)
 {
    unsigned long loops;
    loops = SMBUS_TIMEOUT;
@@ -52,7 +52,7 @@
    } while (--loops);
    return -3;
 }
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
 {
    unsigned char global_status_register;
    unsigned char byte;
@@ -80,9 +80,9 @@
    }
    return byte;
 }
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
    smbus_delay();
@@ -110,7 +110,7 @@
    }
    return 0;
 }
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
 {
    unsigned char global_status_register;
    unsigned char byte;
@@ -142,9 +142,9 @@
 }
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
 {
-	unsigned global_status_register;
+	unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
    smbus_delay();
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index c94722c..0bcf9c5 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -193,8 +193,8 @@
}
-static void rl5c476_set_subsystem(struct device *dev, unsigned vendor,
-				  unsigned device)
+static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor,
+				  unsigned int device)
 {
    u16 miscreg = pci_read_config16(dev, 0x82);
    /* Enable subsystem id register writes */
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
index bfb5ab9..1789f6e 100644
--- a/src/southbridge/ti/pci1x2x/pci1x2x.c
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -38,8 +38,8 @@
    pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
 }
-static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor,
-				     unsigned device)
+static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned int vendor,
+				     unsigned int device)
 {
    /*
     * Enable change sub-vendor ID. Clear the bit 5 to enable to write
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Gerrit-Change-Number: 36333
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth martinroth@google.com
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    