[XS] Change in coreboot[main]: mb/google/brya/gaelin: Enable RTD3 for SSD

[Pranava Y N (Code Review)]

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86647?usp=email )

Change subject: mb/google/brya/gaelin: Enable RTD3 for SSD
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mb/google/brya/gaelin: Enable RTD3 for SSD

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on gaelin and verify that the device
suspends to S0ix.

Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/gaelin/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/86647/1

diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
index af4ff61..014be97 100644
--- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
@@ -70,6 +70,13 @@
    			.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
    	end
    	device ref tcss_xhci on
    		chip drivers/usb/acpi